View CY7C6803312_4799716.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

cy7c68033/cy7c68034 ez-usb ? nx2lp-flex? flexible usb nand flash controller cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 001-04247 rev. *j revised july 6, 2012 ez-usb ? nx2lp-flex? flexible usb nand flash controller cy7c68033/cy7c68034 si licon features certified compliant for bus- or self-powered usb 2.0 operation (tid# 40490118) single-chip, integrated usb 2.0 transceiver and smart sie ultra low power ? 43 ma typical current draw in any mode enhanced 8051 core ? firmware runs from internal ram that is downloaded from nand flash at startup ? no external eeprom required 15 kbytes of on-chip code/data ram ? default nand firmware ? 8 kb ? default free space ? 7 kb four programmable bulk/interrupt/isochronous endpoints ? buffering options: double, triple, and quad additional programmable (bulk/interrupt) 64-byte endpoint smartmedia standard hardware ecc generation with 1-bit correction and 2-bit detection general programmable interface (gpif) ? enables direct connection to most parallel interfaces ? programmable waveform descriptors and configuration registers to define waveforms ? supports multiple ready (rdy) inputs and control (ctl) outputs 12 fully programmable general purpose i/o (gpio) pins integrated, industry -standard enhanced 8051 ? 48-mhz, 24-mhz, or 12-mhz cpu operation ? four clocks for each instruction cycle ? three counter/timers ? expanded interrupt system ? two data pointers 3.3-v operation with 5 v tolerant inputs vectored usb interrupts and gpif/fifo interrupts separate data buffers for the setup and data portions of a control transfer integrated i 2 c controller, runs at 100 or 400 khz four integrated fifos ? integrated glue logic and fifos lower system cost ? automatic conversion to and from 16-bit buses ? master or slave operation ? uses external clock or asynchronous strobes ? easy interface to asic and dsp ics available in space saving 56-pin qfn package cy7c68034 only silicon features ideal for battery powered applications ? suspend current: 100 ? a (typ) cy7c68033 only silicon features ideal for non-battery powered applications ? suspend current: 300 ? a (typ) x 20 pll /0.5 /1.0 /2.0 12/24/48 mhz, four clocks/cycle v cc 1.5k d+ d? address (16)/data bus (8) gpif cy smart usb 1.1/2.0 engine usb 2.0 xcvr additional i/os ctl (3) rdy (2) 8/16 ecc nand boot logic (rom) nx2lp-flex 24 mhz ext. xtal connected for full speed usb integrated full- and high speed xcvr 15 kb ram general programmable i/f to asic/dsp or bus standards such as 8-bit nand, epp, and so on. 4 kb fifo up to 96 mb/s burst rate high-performance, enhanced 8051 core with low power options ?soft configuration? enables easy firmware changes fifo and usb endpoint memory (master or slave modes) enhanced usb core simplifies 8051 code i 2 c master logic block diagram 8051 core
cy7c68033/cy7c68034 document number: 001-04247 rev. *j page 2 of 40 default nand firmware features because the nx2lp-flex ? is intended for nand flash-based usb mass storage applications, a default firmware image is included in the development kit with the following features: high (480 mbps) or full (1 2 mbps) speed usb support nand sizes supported per chip select ? 512 bytes for up to 1 gb capacity ? 2k bytes for up to 8 gb capacity ? 4k bytes for up to 16 gb capacity 12 configurable gpio pins ? two dedicated chip enable (ce#) pins ? six configurable ce#/gpio pins ? up to eight nand flash single-device (single-die) chips are supported ? up to four nand flash dual-device (dual-die) chips are supported ? compile option enables unused ce# pins to be configured as gpios ? four dedicated gpio pins industry standard ecc nand flash correction ? 1 bit for every 256-bit correction ? 2-bit error detection industry standard (smartmedia) page management for wear leveling algorithm, bad block handling, and physical to logical management. 8-bit nand flash interface support support for 30 ns, 50 ns, and 100 ns nand flash timing complies with the usb mass st orage class specification revision 1.0 the default firmware image implements a usb 2.0 nand flash controller. this controller adheres to the mass storage class bulk-only transport specification . the usb port of the nx2lp-flex is connected to a host computer directly or through the downstream port of a usb hub. the host software issues commands and data to the nx2lp- flex and receives status and data from the nx2lp-flex using standard usb protocol. the default firmware image supports industry leading 8-bit nand flash interfaces and both common nand page sizes of 512 and 2k bytes. up to eight ce# pins enable the nx2lp-flex to be connected to up to eight single or four dual-die nand flash chips. complete source code and documentation for the default firmware image are included in the nx2lp-flex development kit to enable customization for meeting design requirements. additionally, compile options for the default firmware enable quick configuration of some features to decrease design effort and increase time-to-market advantages.
cy7c68033/cy7c68034 document number: 001-04247 rev. *j page 3 of 40 contents overview ............................................................................ 4 applications ...................................................................... 4 functional overview ........................................................ 4 usb signaling speed ............. .............. .............. ......... 4 8051 microprocessor ... .............. .............. ........... ......... 4 i2c bus ........................................................................ 5 buses .......................................................................... 6 enumeration ................................................................ 6 default silicon id values ............................................. 7 renumeration? ..................... ..................................... 7 bus-powered applications ... ........................................ 7 interrupt system .......................................................... 7 reset and wakeup ...................................................... 9 program/data ram ................................................... 10 register addresses ................................................... 10 endpoint ram ........................................................... 11 external fifo interface ............................................. 13 gpif .......................................................................... 13 ecc generation ........................................................ 13 autopointer access ................................................... 14 i2c controller ............................................................ 14 pin assignments ............................................................ 15 register summary .......................................................... 21 absolute maximum ratings .......................................... 28 operating conditions ..................................................... 28 dc characteristics ......................................................... 28 usb transceiver ....................................................... 28 ac electrical characteristics ........................................ 28 usb transceiver ....................................................... 28 slave fifo asynchronous r ead ............ ........... ........ 29 slave fifo asynchronous write ............................... 29 slave fifo asynchronous packet end strobe ......... 30 slave fifo output enable ........................................ 30 slave fifo address to flags/data ............................ 31 slave fifo asynchronous address .......................... 31 sequence diagram .................................................... 32 ordering information ...................................................... 34 ordering code definitions ..... .................................... 34 package diagrams .......................................................... 35 pcb layout recommendations .................................... 36 quad flat package no leads (qfn) package design notes ................................................................... 36 acronyms ........................................................................ 38 document conventions ................................................. 38 units of measure ....................................................... 38 document history page ................................................. 39 sales, solutions, and legal information ...................... 40 worldwide sales and design s upport ......... .............. 40 products .................................................................... 40 psoc solutions ......................................................... 40
cy7c68033/cy7c68034 document number: 001-04247 rev. *j page 4 of 40 overview cypress semiconductor corporation?s ez-usb ? nx2lp-flex (cy7c68033/cy7c68034) is a firmware-based, programmable version of the ez-usb nx2lp ? (cy7c68023/cy7c68024), which is a fixed-function, low power usb 2.0 nand flash controller. by integrating the usb 2.0 transceiver, serial interface engine (sie), enhanced 8051 microcontroller, and a program- mable peripheral interface in a single chip, cypress has created a very cost-effective solution that enables feature-rich nand flash-based applications. the ingenious architecture of nx2lp-flex results in usb data transfer rates of over 53 mbytes per second, the maximum allowable usb 2.0 bandwidth, while still using a low cost 8051 microcontroller in a small 56-pin qfn package. because it incorporates the usb 2.0 transceiver, the nx2lp-flex is more economical, providing a smaller footprint solution than external usb 2.0 sie or transceiver implementations. with ez-usb nx2lp-flex, the cypress smart sie handles most of the usb 1.1 and 2.0 protocol, freeing the embedded microcontroller for application-specific functions and decreasing development time while ensuring usb compatibility. the gpif and master/slave endpoint fifo (8- or 16-bit data bus) provide an easy and glueless interface to popular interfaces such as utopia, epp, i 2 c, pcmcia, and most dsp processors. applications the nx2lp-flex enables designers to add extra functionality to basic nand flash mass storage designs, or to interface them with other peripheral devices. applications may include: nand flash-based gps devices nand flash-based dvb video capture devices wireless pointer/presenter tools with nand flash storage nand flash-based mpeg/tv conversion devices legacy conversion devices with nand flash storage nand flash-based cameras nand flash mass storage device with biometric (for example, fingerprint) security home pna devices with nand flash storage wireless lan with nand flash storage nand flash-based mp3 players lan networking with nand flash storage figure 1. exampl e dvb block diagram figure 2. example gps block diagram the ? reference designs ? section of the cypress web site provides additional tools for typical usb 2.0 applications. each reference design comes complete with firmware source and object code, schemati cs, and documentation. functional overview usb signaling speed nx2lp-flex operates at two of t he three rates defined in the usb specification revision 2. 0, dated april 27, 2000: full speed, with a signaling bit rate of 12 mbps high speed, with a signaling bit rate of 480 mbps. nx2lp-flex does not support the low speed signaling mode of 1.5 mbps. 8051 microprocessor the 8051 microprocessor embedded in the nx2lp-flex has 256 bytes of register ram, an expanded interrupt system and three timer/counters. lcd nx2lp- flex buttons dvb decoder nand bank(s) ce[7:0] ctl i/o i/o d+/- i/o i/o nand-based dvb unit audio / video i/o nx2lp- flex buttons gps nand bank(s) ce[7:0] ctl i/o d+/- i/o i/o nand-based gps unit lcd i/o
cy7c68033/cy7c68034 document number: 001-04247 rev. *j page 5 of 40 8051 clock frequency nx2lp-flex has an on-chip oscillator circuit that uses an external 24 mhz (100 ppm) crystal with the following characteristics: parallel resonant fundamental mode 500 ? w drive level 12 pf (5% tolerance) load capacitors. an on-chip pll multiplies the 24-mhz oscillator up to 480 mhz, as required by the transceiver/p hy, and internal counters divide it down for use as the 8051 clock. the default 8051 clock frequency is 12 mhz. the clock frequency of the 8051 can be changed by the 8051 through the cpucs register, dynamically figure 3. crystal configuration special function registers certain 8051 sfr addresses are populated to provide fast access to critical nx2lp-flex functions. these sfr additions are shown in table 1 on page 6 . bold type indicates non-standard, enhanced 8051 registers. the two sfr rows that end with ?0? and ?8? contain bit-addr essable registers. the four i/o ports a?d use the sfr addresses used in the standard 8051 for ports 0?3, which are not implemented in nx2lp-flex. because of the faster and more efficient sfr addressing, the nx2lp-flex i/o ports are not addressable in external ram space (using the movx instruction). i 2 c bus nx2lp supports the i 2 c bus as a master only at 100/400 khz. scl and sda pins have open-drain outputs and hysteresis inputs. these signals must be pulled up to 3.3 v, even if no i 2 c device is connected. the i 2 c bus is disabled at startup and only available for use after the initial nand access. 12 pf 12 pf 24 mhz 20 pll c1 c2 12-pf capacitor values assumes a trace capacitance of 3 pf per side on a four-layer fr4 pca
cy7c68033/cy7c68034 document number: 001-04247 rev. *j page 6 of 40 buses the nx2lp-flex features an 8- or 16-bit ?fifo? bidirectional data bus, multiplexed on i/o ports b and d. the default firmware image implements an 8-bit data bus in gpif mast er mode. it is recommended th at additional interfaces added to the default firmware image use this 8-bit data bus. enumeration during the startup sequ ence, internal logic checks for the presence of nand flash with valid firmware. if valid firmware is fou nd, the nx2lp-flex loads it and operates according to the firmware. if no nand flash is detected, or if no valid firmware is found, the nx2lp-flex uses the default values from internal rom space fo r manufacturing mode operation. the two modes of operation are described in the section normal operation mode on page 7 and manufacturing mode on page 7 . table 1. special function registers x 8x 9x ax bx cx dx ex fx 0 ioa iob ioc iod scon1 psw acc b 1sp exif int2clr ioe sbuf1 2dpl0 mpage int4clr oea 3dph0 oeb 4 dpl1 oec 5 dph1 oed 6 dps oee 7pcon 8 tcon scon0 ie ip t2con eicon eie eip 9 tmod sbuf0 atl0 autoptrh1 ep2468stat ep01stat rcap2l btl1 autoptrl1 ep24fifoflgs gpiftrig rcap2h cth0 reserved ep68fifoflgs tl2 dth1 autoptrh2 gpifsgldath th2 e ckcon autoptrl2 gpifsgldatlx f reserved autoptrsetup gpifsgldatlnox
cy7c68033/cy7c68034 document number: 001-04247 rev. *j page 7 of 40 figure 4. nx2lp-flex enumeration sequence normal operation mode in normal operation mode, the nx2lp-flex behaves as a usb 2.0 mass storage class nand flash controller. this includes all typical usb device states (powered, configured, and so on). the usb descriptors are returned according to the data stored in the configuration data memory area. normal read and write access to the nand flash is available in this mode. manufacturing mode in manufacturing mode, the nx2l p-flex enumerates using the default descriptors and configuration data that are stored in internal rom space. this mode enables for first time programming of the configurati on data memory area, and board level manufacturing tests. default silicon id values to facilitate proper usb enumeration when no programmed nand flash is present, the nx 2lp-flex has default silicon id values stored in rom space. the default silicon id values should only be used for development purposes. designers must use their own vendor id for final products. a vendor id is obtained through registration with the usb implementor?s forum (usb-if). if the nx2lp-flex is used as a mass storage class device, a unique usb serial number is required for each device to comply with the usb mass storage class specification. cypress provides all the software tools and drivers necessary to properly programme and test the nx2lp-flex. refer to the documentation in the development kit for more information on these topics. renumeration? cypress?s renumeration feature is used in conjunction with the nx2lp-flex manufacturing software tools to enable first-time nand programming. it is only available when used in conjunction with the nx2lp-flex manufacturing tools, and is not enabled during normal operation. bus-powered applications the nx2lp-flex fully supports bus-powered designs by enumerating with less than 100 ma , as required by the usb 2.0 specification. interrupt system int2 interrupt request and enable registers nx2lp-flex implements an autovector feature for int2 and int4. there are 27 int2 (usb) vectors and 14 int4 (fifo/gpif) vectors. for mo re details, refer to the ez-usb technical reference manual (trm) . usb-interrupt autovectors the main usb interrupt is shared by 27 interrupt sources. to save the code and processing time normally required to identify the individual usb interrupt source, the nx2lp-flex provides a second level of interrupt vector ing, called autovectoring. when a usb interrupt is asserted, the nx2lp-flex pushes the program counter to its stack and then ju mps to address 0x0500; it expects to find a ?jump? instruction to the usb interrupt service routine here. developers familiar with cypress?s programmable usb devices should note that these interrupt vector values differ from those used in other ez-usb microcontrollers. this is due to the additional nand boot logic that is present in the nx2lp-flex rom space. also, these values are fixed and cannot be changed in the firmware. nand flash programmed? load default descriptors and configuration data manufacturing mode load firmware from nand enumerate according to firmware normal operation mode start-up enumerate as unprogrammed nx2lp-flex nand flash present? no yes yes no table 2. default silicon id values default vid/pid/did vendor id 0x04b4 cypress semiconductor product id 0x8613 ez-usb ? default device release 0xannn depends on chip revision (nnn = chip revision, where first silicon = 001)
cy7c68033/cy7c68034 document number: 001-04247 rev. *j page 8 of 40 if autovectoring is enabled (av2en = 1 in the intset-up register ), the nx2lp-flex substitutes its int2vec byte. therefore, if t he high byte (?page?) of a jump-table address is preloaded at location 0x544, the automatically insert ed int2vec byte at 0x545 dir ects the jump to the correct address out of the 27 addresses within the page. fifo/gpif interrupt (int4) just as the usb interrupt is shared among 27 individual usb-inte rrupt sources, the fifo/gpif interrupt is shared among 14 indiv idual fifo/gpif sources. the fifo/gpif interrupt, such as the usb interrupt, can employ autovectoring. table 4 on page 9 shows the priority and int4vec values for the 14 fifo/gpif interrupt sources. table 3. int2 usb interrupts usb interrupt table for int2 priority int2vec value source notes 1 0x500 sudav setup data available 2 0x504 sof start of frame (or microframe) 3 0x508 sutok setup token received 4 0x50c suspend usb suspend request 5 0x510 usb reset bus reset 6 0x514 hispeed entered high speed operation 7 0x518 ep0ack nx2lp ack?d the control handshake 8 0x51c reserved 9 0x520 ep0-in ep0-in ready to be loaded with data 10 0x524 ep0-out ep0-out has usb data 11 0x528 ep1-in ep1-in ready to be loaded with data 12 0x52c ep1-out ep1-out has usb data 13 0x530 ep2 in: buffer available. out: buffer has data 14 0x534 ep4 in: buffer available. out: buffer has data 15 0x538 ep6 in: buffer available. out: buffer has data 16 0x53c ep8 in: buffer available. out: buffer has data 17 0x540 ibn in-bulk-nak (any in endpoint) 18 0x544 reserved 19 0x548 ep0ping ep0 out was pinged and it nak?d 20 0x54c ep1ping ep1 out was pinged and it nak?d 21 0x550 ep2ping ep2 out was pinged and it nak?d 22 0x554 ep4ping ep4 out was pinged and it nak?d 23 0x558 ep6ping ep6 out was pinged and it nak?d 24 0x55c ep8ping ep8 out was pinged and it nak?d 25 0x560 errlimit bus errors exceeded the programmed limit 26 0x564 reserved 27 0x568 reserved 28 0x56c reserved 29 0x570 ep2isoerr iso ep2 out pid sequence error 30 0x574 ep4isoerr iso ep4 out pid sequence error 31 0x578 ep6isoerr iso ep6 out pid sequence error 32 0x57c ep8isoerr iso ep8 out pid sequence error
cy7c68033/cy7c68034 document number: 001-04247 rev. *j page 9 of 40 if autovectoring is enabled (av4en = 1 in the intset-up register), the nx2lp-flex su bstitutes its int4vec byte. therefore, if the high byte (?page?) of a jump-table address is preloaded at location 0x554, the automatically inserted int4vec byte at 0x555 directs the jump to the correct address out of the 14 addresses within the page. when the isr occurs, the nx2lp-flex pushes the program counter to its stack and then jumps to address 0x553; it expects to find a ?jump? instruction to the isr interrupt service routine here. reset and wakeup reset pin the input pin reset#, resets the nx2lp-flex when asserted. this pin has hysteresis and is active low. when a crystal is used as the clock source for the nx2lp-flex, the reset period must enable the stabilization of the crystal and the pll. this reset period should be approximately 5 ms after v cc has reached 3.0v. if the crystal input pin is driven by a clock signal, the internal pll stabilizes in 200 ? s after v cc has reached 3.0 v [1] . figure 5 shows a por condition and a reset applied during operation. a por is defined as the time reset is asserted while power is being applied to the circuit. a powered reset is defined to be when the nx2lp-flex has previously been powered on and operat ing and the reset# pin is asserted. for more information on power on reset implementation for the ez-usb family of products, refer to the application note ez-usb fx2?/at2?/sx2?. table 4. individual fifo/gpif interrupt sources priority int4vec value source notes 1 0x580 ep2pf endpoint 2 programmable flag 2 0x584 ep4pf endpoint 4 programmable flag 3 0x588 ep6pf endpoint 6 programmable flag 4 0x58c ep8pf endpoint 8 programmable flag 5 0x590 ep2ef endpoint 2 empty flag 6 0x594 ep4ef endpoint 4 empty flag 7 0x598 ep6ef endpoint 6 empty flag 8 0x59c ep8ef endpoint 8 empty flag 9 0x5a0 ep2ff endpoint 2 full flag 10 0x5a4 ep4ff endpoint 4 full flag 11 0x5a8 ep6ff endpoint 6 full flag 12 0x5ac ep8ff endpoint 8 full flag 13 0x5b0 gpifdone gpif operation complete 14 0x5b4 gpifwf gpif waveform figure 5. reset timing plots v il 0 v 3.3 v 3.0 v t reset v cc reset# power-on reset t reset v cc reset# v il powered reset 3.3 v 0 v note 1. if the external clock is powered at the sa me time as the cy7c68033/cy7c68034 and ha s a stabilization wait period, it must be added to the 200 ? s.
cy7c68033/cy7c68034 document number: 001-04247 rev. *j page 10 of 40 wakeup pins the 8051 puts itself and the rest of the chip into a power down mode by setting pcon.0 = 1. th is stops the oscillator and pll. when wakeup is asserted by external logic, the oscillator restarts, after the pll stabilizes, and then the 8051 receives a wakeup interrupt. this applies whether or not nx2lp-flex is connected to the usb. the nx2lp-flex exits the power down (usb suspend) state using one of the following methods: usb bus activity (if d+/d? lines are left floating, noise on these lines may indicate activity to the nx2lp-flex and initiate a wakeup). external logic asserts the wakeup pin external logic asserts the pa3/wu2 pin. the second wakeup pin, wu2, can also be configured as a gpio pin. this enables a simple external r-c network to be used as a periodic wakeup source. note th at wakeup is, by default, active low. program/data ram internal rom/ram size the nx2lp-flex has 1 kbytes rom and 15 kbytes of internal program/data ram, where psen# /rd# signals are internally ored to enable the 8051 to access it as both program and data memory. no usb control registers appear in this space. internal code memory this mode implements the intern al block of ram (starting at 0x0500) as combined code and data memory, as shown in figure 6 . only the internal and scratch pad ram spaces have the following access: usb download (only supported by the cypress manufacturing tool) setup data pointer nand boot access. figure 6. internal code memory register addresses figure 7. internal register addresses table 5. reset timing values condition t reset power-on reset with crystal 5 ms power-on reset with external clock source 200 ? s + clock stability time powered reset 200 ? s *sudptr, usb download, nand boot access ffff e200 e1ff e000 3fff 0000 7.5 kbytes usb registers and 4 kbytes fifo buffers (rd#, wr#) 512 bytes ram data (rd#, wr#)* 15 kbytes ram code and data (psen#, rd#, wr#)* 0500 1 kbyte rom ffff e800 e7bf e740 e73f e700 e6ff e500 e4ff e480 e47f e400 e200 e1ff e000 e3ff efff 2 kbytes reserved 64 bytes ep0 in/out 64 bytes reserved 8051 addressable registers reserved (128) 128 bytes gpif waveforms 512 bytes 8051 xdata ram f000 (512) reserved (512) e780 64 bytes ep1out e77f 64 bytes ep1in e7ff e7c0 4 kbytes ep2-ep8 buffers (8 512)
cy7c68033/cy7c68034 document number: 001-04247 rev. *j page 11 of 40 endpoint ram size 3 64 bytes (endpoints 0 and 1) 8 512 bytes (endpoints 2, 4, 6, 8) organization ep0 ? bidirectional endpoint zero, 64-byte buffer ep1in, ep1out ? 64-byte buffers, bulk or interrupt ep2, 4, 6, 8 ? eight 512-byte buffers, bulk, interrupt, or isochronous. ? ep4 and ep8 can be double buffered, while ep2 and 6 can be either double, triple, or quad buffered. for high speed endpoint configuration options, see figure 8 . setup data buffer a separate 8-byte buffer at 0xe6b8-0xe6bf holds the setup data from a control transfer. endpoint configurations (high speed mode) endpoints 0 and 1 are the same for every configuration. endpoint 0 is the only control endpoint, and endpoint 1 can be either bulk or interrupt. the endpoint buffers can be configured in any 1 of the 12 configurations shown in the vertical columns. when operating in full speed bulk mode, only the first 64 bytes of each buffer are used. for example, in high speed the max packet size is 512 bytes, but in full speed it is 64 bytes. even though a buffer is configured to be a 512 byte buffer, in full speed only the first 64 bytes are used. the unused endpoint buffer space is not available for other operations. the following is an example endpoint configuration: ep2?1024 double buffered; ep6?512 quad buffered (column 8 in figure 8 ). figure 8. endpoint configuration 64 64 64 512 512 1024 1024 1024 1024 1024 1024 1024 512 512 512 512 512 512 512 512 512 512 ep2 ep2 ep2 ep6 ep6 ep8 ep8 ep0 in&out ep1 in ep1 out 1024 1024 ep6 1024 512 512 ep8 512 512 ep6 512 512 512 512 ep2 512 512 ep4 512 512 ep2 512 512 ep4 512 512 ep2 512 512 ep4 512 512 ep2 512 512 512 512 ep2 512 512 512 512 ep2 512 512 1024 ep2 1024 1024 ep2 1024 1024 ep2 1024 512 512 ep6 1024 1024 ep6 512 512 ep8 512 512 ep6 512 512 512 512 ep6 1024 1024 ep6 512 512 ep8 512 512 ep6 512 512 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 1 2 3 4 5 6 7 8 9 10 11 12
cy7c68033/cy7c68034 document number: 001-04247 rev. *j page 12 of 40 default full speed alternate settings default high speed alternate settings table 6. default full speed alternate settings [2, 3] alternate setting 0 1 2 3 ep0 64 64 64 64 ep1out 0 64 bulk 64 int 64 int ep1in 0 64 bulk 64 int 64 int ep2 0 64 bulk out (2) 64 int out (2) 64 iso out (2) ep4 0 64 bulk out (2) 64 bulk out (2) 64 bulk out (2) ep6 0 64 bulk in (2) 64 int in (2) 64 iso in (2) ep8 0 64 bulk in (2) 64 bulk in (2) 64 bulk in (2) table 7. default high speed alternate settings [2, 3] alternate setting 0 1 2 3 ep0 64 64 64 64 ep1out 0 512 bulk [4] 64 int 64 int ep1in 0 512 bulk [4] 64 int 64 int ep2 0 512 bulk out (2) 512 int out (2) 512 iso out (2) ep4 0 512 bulk out (2) 512 bulk out (2) 512 bulk out (2) ep6 0 512 bulk in (2) 512 int in (2) 512 iso in (2) ep8 0 512 bulk in (2) 512 bulk in (2) 512 bulk in (2) notes 2. ?0? means ?not implemented.? 3. ?2? means ?double buffered.? 4. even though these buffers are 64 bytes, they are reported as 512 for usb 2.0 compliance. the user must never transfer packets larger than 64 bytes to ep1.
cy7c68033/cy7c68034 document number: 001-04247 rev. *j page 13 of 40 external fifo interface architecture the nx2lp-flex slave fifo architecture has eight 512-byte blocks in the endpoi nt ram that directly serve as fifo memories, and are controlled by fifo control signals (such as slcs#, slrd, slwr, sloe , pktend, and flags). in operation, some of the eight ra m blocks fill or empty from the sie, while the others are connect ed to the i/o transfer logic. the transfer logic takes two forms: the gpif for internally generated control signals or the slave fifo interface for externally controlled transfers. master/slave control signals the nx2lp-flex endpoint fifos are implemented as eight physically distinct 256 16 ram blocks. the 8051/sie can switch any of the ram blocks between two domains, the usb (sie) domain and the 8051-i/o unit domain. this switching is done virtually instantaneously, giving essentially zero transfer time between ?usb fifos? and ?slave fifos?. since they are physically the same me mory, no bytes are actually transferred between buffers. at any time, some ram blocks ar e filling/emptying with usb data under sie control, while other ram blocks are available to the 8051 and/or the i/o control uni t. the ram blocks operate as single-port in the usb domain and dual-port in the 8051-i/o domain. the blocks can be configured as single, double, triple, or quad buffered as previously shown. the i/o control unit implements either an internal-master (m for master) or external-master (s for slave) interface. in master (m) mode, the gpif in ternally contro ls fifoadr[1:0] to select a fifo. the two rdy pins can be used as flag inputs from an external fifo or other logic if desired. the gpif can be run from an internally derived clock (ifclk), at a rate that transfers data up to 96 megabytes/s (48 mhz ifclk with 16-bit interface). in slave (s) mode, the nx2lp-flex accepts an internally derived clock (ifclk, max. frequency 48 mhz) and slcs#, slrd, slwr, sloe, pktend signals fr om external logic. each endpoint can individually be selected for byte or word operation by an internal configuration bit and a slave fifo output enable signal sloe enables data of the selected width. external logic must ensure that the output enable signal is inactive when writing data to a slave fifo. the slave interface must operate asynchronously, where the slrd and slwr signals act directly as strobes, rather than a clock qualifier as in a synchronous mode. the signals slrd, slwr, sloe and pktend are gated by the signal slcs#. gpif and fifo clock rates an 8051 register bit selects one of two frequencies for the internally supplied interface clock: 30 mhz and 48 mhz. a bit within the ifconfig register inverts the ifclk signal. the default nand firmware image implements a 48 mhz internally supplied interface clock. the nand boot logic uses the same configuration to implem ent 100-ns timing on the nand bus to support proper detection of all nand flash types. gpif the gpif is a flexible 8- or 16-bit parallel interface driven by a user-programmable finite state machine. it enables the nx2lp-flex to perform local bus mastering and can implement a wide variety of protocols such as 8-bit nand interface, printer parallel port, and utopia. the default nand firmware and boot logic uses gpif functionality to interface with nand flash. the gpif on the nx2lp-flex features three programmable control outputs (ctl) and two general purpose ready inputs (rdy). the gpif data bus width can be 8 or 16 bits. because the default nand firmware image implements an 8-bit data bus and up to eight chip enable pins on the gpif ports, it is recommended that designs bas ed upon the default firmware image also use an 8-bit data bus. each gpif vector defines the state of the control outputs and determines what state a ready input (or multiple inputs) must be before proceeding. the gpif vector can be programmed to advance a fifo to the next data value, advance an address, and so on. a sequence of the gpif vectors make up a single waveform that is executed to perform the desired data move between the nx2lp-flex and the external device. three control out signals the nx2lp-flex exposes three c ontrol signals, ctl[2:0]. ctlx waveform edges can be programmed to make transitions as fast as once per clock (20.8 ns using a 48 mhz clock). two ready in signals the 8051 programs the gpif unit to test the rdy pins for gpif branching. the 56-pin package br ings out two signals, rdy[1:0]. long transfer mode in gpif master mode, the 8051 appropriately sets gpif transaction count registers (g piftcb3, gpiftc b2, gpiftcb1, or gpiftcb0) for unattended transfers of up to 2 32 transactions. the gpif automatically throttles data flow to prevent underflow or overflow until the full nu mber of requested transactions complete. the gpif decrements the value in these registers to represent the current stat us of the transaction. ecc generation [5] the nx2lp-flex can calculate error correcting codes (eccs) on data that passes across its gpif or slave fifo interfaces. there are two ecc configurations: two eccs, each calculated ov er 256 bytes (smartmedia standard) one ecc calculated over 512 bytes. the following two ecc configuratio ns are selected by the eccm bit. the ecc can correct any one-bit error or detect any two-bit error. note 5. to use the ecc logic, the gpif or slave fifo in terface must be configured for byte-wide operation.
cy7c68033/cy7c68034 document number: 001-04247 rev. *j page 14 of 40 eccm = 0 two 3-byte eccs, each calculated over a 256-byte block of data. this configuration conforms to the smartmedia standard and is used by both the nand boot logic and default nand firmware image. when any value is written to eccreset and data is then passed across the gpif or slave fifo interface, the ecc for the first 256 bytes of data is calculated and stored in ecc1. the ecc for the next 256 bytes of data is stored in ecc2. after the second ecc is calculated, the values in the eccx registers do not change until eccreset is writt en again, even if more data is subsequently passed across the interface. eccm = 1 one 3-byte ecc calculated over a 512-byte block of data. when any value is written to eccreset and data is then passed across the gpif or slave fifo interface, the ecc for the first 512 bytes of data is calculated and stored in ecc1; ecc2 is unused. after the ecc is calc ulated, the value in ecc1 does not change until eccreset is writ ten again, even if more data is subsequently passed across the interface autopointer access nx2lp-flex provides two identical autopointers. they are similar to the internal 8051 data pointers, but with an additional feature: they can optionally increment after every memory access. also, the autopointers can point to any nx2lp-flex register or endpoint buffer space. i 2 c controller nx2lp has one i 2 c port that the 8051, once running uses to control external i 2 c devices. the i 2 c port operates in master mode only. the i 2 c post is disabled at startup and only available for use after the initial nand access. i 2 c port pins the i 2 c pins scl and sda must have external 2.2-k ? pull up resistors even if no eeprom is connected to the nx2lp. i 2 c interface general-purpose access the 8051 can control peripherals connected to the i 2 c bus using the i 2 ctl and i 2 data registers. nx2lp provides i 2 c master control only and is never an i 2 c slave.
cy7c68033/cy7c68034 document number: 001-04247 rev. *j page 15 of 40 pin assignments figure 9 and figure 10 on page 16 identify all signals for the 56-pin nx2lp-flex package. three modes of operation are available for the nx2lp-flex: port mode, gpif master mode, and slave fifo mode. these modes define the signals on the right edge of each column in figure 9 . the right-most column details t he signal functionality from the default nand firmware image, wh ich actually utilizes gpif master mode. the signals on the left edge of the ?port? column are common to all modes of the nx2lp-flex. the 8051 selects the interface mode using the ifconfig[1:0] register bits. port mode is the power-on default configuration. figure 10 on page 16 details the pinout of the 56-pin package and lists pin names for all modes of operation. pin names with an asterisk (*) feature programmable polarity. figure 9. port and signal mapping xtalin xtalout reset# wakeup# scl sdata dplus dminus ?? rdy0 ?? rdy1 ?? ctl0 ?? ctl1 ? ctl2 ?? pa7 ?? pa6 ? pa5 ?? pa4 ? pa3/wu2 ? pa2 ? pa1/int1# ? pa0/int0# ?? gpio8 ?? gpio9 ?? fd[15] ?? fd[14] ?? fd[13] ?? fd[12] ?? fd[11] ?? fd[10] ?? fd[9] ?? fd[8] ?? fd[7] ?? fd[6] ?? fd[5] ?? fd[4] ?? fd[3] ?? fd[2] ?? fd[1] ?? fd[0] ?? slrd ?? slwr ?? flaga ?? flagb ?? flagc ?? flagd/slcs#/pa7 ?? pktend ?? fifoadr1 ?? fifoadr0 ?? pa3/wu2 ?? sloe ?? pa1/int1# ?? pa0/int0# ?? gpio8 ?? gpio9 ?? fd[15] ?? fd[14] ?? fd[13] ?? fd[12] ?? fd[11] ?? fd[10] ?? fd[9] ?? fd[8] ?? fd[7] ?? fd[6] ?? fd[5] ?? fd[4] ?? fd[3] ?? fd[2] ?? fd[1] ?? fd[0] pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0 pb7 pb6 pb5 pb4 pb3 pb2 pb1 pb0 pa7 pa6 pa5 pa4 wu2/pa3 pa2 int1#/pa1 into#/pa0 gpio8 gpio9 port gpif master slave fifo default nand ?? ce7#/gpio7 ?? ce6#/gpio6 ?? ce5#/gpio5 ?? ce4#/gpio4 ?? ce3#/gpio3 ?? ce2#/gpio2 ?? ce1# ?? ce0# ?? dd7 ?? dd6 ?? dd5 ?? dd4 ?? dd3 ?? dd2 ?? dd1 ?? dd0 ? r_b1# ?? r_b2# ?? we# ?? re0# ?? re1# ?? gpio1 ?? gpio0 ?? wp_sw# ?? wp_nf# ?? led2# ?? led1# ?? ale ?? cle ?? gpio8 ?? gpio9 firmware use
cy7c68033/cy7c68034 document number: 001-04247 rev. *j page 16 of 40 figure 10. cy7c68033/cy7c68034 56-pin qfn pin assignment 28 27 26 25 24 23 22 21 20 19 18 17 16 15 43 44 45 46 47 48 49 50 51 52 53 54 55 56 1 2 3 4 5 6 7 8 9 10 11 12 13 14 42 41 40 39 38 37 36 35 34 33 32 31 30 29 reset# gnd pa7/*flagd/slcs# pa6/*pktend pa5/fifoadr1 pa4/fifoadr0 pa3/*wu2 pa2/*sloe pa1/int1# pa0/int0# vcc ctl2/*flagc ctl1/*flagb ctl0/*flaga rdy0/*slrd rdy1/*slwr avcc xtalout xtalin agnd avcc dplus dminus agnd vcc gnd gpio8 reserved# vcc *wakeup pd0/fd8 pd1/fd9 pd2/fd10 pd3/fd11 pd4/fd12 pd5/fd13 pd6/fd14 pd7/fd15 gnd gpio9 vcc gnd gnd vcc gnd pb7/fd7 pb6/fd6 pb5/fd5 pb4/fd4 pb3/fd3 pb2/fd2 pb1/fd1 pb0/fd0 vcc sdata scl
cy7c68033/cy7c68034 document number: 001-04247 rev. *j page 17 of 40 table 8. nx2lp-flex pin descriptions [6] 56-pin qfn pin number default pin name nand firmware usage pin type default state description 9 dminus n/a i/o/z z usb d? signal . connect to the usb d? signal. 8 dplus n/a i/o/z z usb d+ signal . connect to the usb d+ signal. 42 reset# n/a input n/a active low reset . resets the entire chip. see section reset and wakeup on page 9 for more details. 5 xtalin n/a input n/a crystal input . connect this signal to a 24 mhz parallel-resonant, fundamental mode crystal and load capacitor to gnd. it is also correct to drive xtalin with an external 24 mhz square wave derived from another clock source. when driving from an external source, the driving signal should be a 3.3 v square wave. 4 xtalout n/a output n/a crystal output . connect this signal to a 24 mhz parallel-resonant, fundamental mode crystal and load capacitor to gnd. if an external clock is used to drive xtalin, leave this pin open. 54 gpio9 gpio9 o/z 12 mhz gpio9 is a bidirectional i/o port pin. 1 rdy0 or slrd r_b1# input n/a multiplexed pin wh ose function is select ed by ifconfig[1:0]. rdy0 is a gpif input signal. slrd is the input-only read st robe with programmable polarity (fifopinpolar[3]) for the slave fifos connected to fd[7:0] or fd[15:0]. r_b1# is a nand ready/busy input signal. 2 rdy1 or slwr r_b2# input n/a multiplexed pin wh ose function is select ed by ifconfig[1:0]. rdy1 is a gpif input signal. slwr is the input-only write strobe with programmable polarity (fifopinpolar[2]) for the slave fifos connected to fd[7:0] or fd[15:0]. r_b2# is a nand ready/busy input signal. 29 ctl0 or flaga we# o/z h multiplexed pin whose functi on is selected by ifconfig[1:0]. ctl0 is a gpif control output. flaga is a programmable slave-fifo output status flag signal. defaults to programmable for the fifo selected by the fifoadr[1:0] pins. we# is the nand write enable output signal. 30 ctl1 or flagb re0# o/z h multiplexed pin whose functi on is selected by ifconfig[1:0]. ctl1 is a gpif control output. flagb is a programmable slave-fifo output status flag signal. defaults to full for th e fifo selected by the fifoadr[1:0] pins. re0# is a nand read enable output signal. 31 ctl2 or flagc re1# o/z h multiplexed pin whose functi on is selected by ifconfig[1:0]. ctl2 is a gpif control output. flagc is a programmable slave-fifo output status flag signal. defaults to empty for the fifo selected by the fifoadr[1:0] pins. re1# is a nand read enable output signal. note 6. unused inputs should not be left floating. tie either high or low as appropriate. outputs should only be pulled up or down to ensure signals at power up and in standby. note also that no pins should be driven while the device is powered down.
cy7c68033/cy7c68034 document number: 001-04247 rev. *j page 18 of 40 13 gpio8 gpio8 i/o/z i gpio8: is a bidirectional i/o port pin. 14 reserved# n/a input n/a reserved . connect to ground. 15 scl n/a od z clock for the i 2 c interface. connect to vcc with a 2.2k resistor, even if no i 2 c peripheral is attached. 16 sdata n/a od z data for the i 2 c interface. connect to vc c with a 2.2k resistor, even if no i 2 c peripheral is attached. 44 wakeup unused input n/a usb wakeup . if the 8051 is in suspend, asserting this pin starts up the oscillator and interrupts the 8051 to allow it to exit the suspend mode. holding wakeup asserted inhibits the ez-usb chip from suspending. this pin has programmable polarity, controlled by wakeup[4]. port a 33 pa0 or int0# cle i/o/z i (pa0) multiplexed pin whose function is selected by portacfg[0] pa0 is a bidirectional i/o port pin. int0# is the active-low 8051 int0 interrupt input signal, which is either edge triggered (it0 = 1) or level triggered (it0 = 0). cle is the nand command latch enable signal. 34 pa1 or int1# ale i/o/z i (pa1) multiplexed pin whose function is selected by portacfg[1] pa1 is a bidirectional i/o port pin. int1# is the active-low 8051 int1 interrupt input signal, which is either edge triggered (it1 = 1) or level triggered (it1 = 0). ale is the nand address latch enable signal. 35 pa2 or sloe led1# i/o/z i (pa2) multiplexed pi n whose function is sele cted by ifconfig[1:0]. pa2 is a bidirectional i/o port pin. sloe is an input-only output enab le with programmable polarity (fifopinpolar[4]) for the slave fifos connected to fd[7:0] or fd[15:0]. led1# is the data activity indicator led sink pin. 36 pa3 or wu2 led2# i/o/z i (pa3) mul tiplexed pin whose function is selected by wakeup[7] and oea[3] pa3 is a bidirectional i/o port pin. wu2 is an alternate source for usb wakeup, enabled by wu2en bit (wakeup[1]) and polarity set by wu2pol (wakeup[4]). if the 8051 is in suspend and wu2en = 1, a transition on this pin starts up the oscillator and interrupts the 8051 to allow it to exit the suspend mode. asserting this pin inhibits the chip from suspending, if wu2en = 1. led2# is the chip activity indicator led sink pin. 37 pa4 or fifoadr0 wp_nf# i/o/z i (pa4) multiplexed pin whose function is selected by ifconfig[1:0]. pa4 is a bidirectional i/o port pin. fifoadr0 is an input-only address select for the slave fifos connected to fd[7:0] or fd[15:0]. wp_nf# is the nand write-protec t control output signal. 38 pa5 or fifoadr1 wp_sw# i/o/z i (pa5) multiplexed pin whose function is selected by ifconfig[1:0]. pa5 is a bidirectional i/o port pin. fifoadr1 is an input-only address select for the slave fifos connected to fd[7:0] or fd[15:0]. wp_sw# is the nand write-protec t switch input signal. table 8. nx2lp-flex pin descriptions (continued) [6] 56-pin qfn pin number default pin name nand firmware usage pin type default state description
cy7c68033/cy7c68034 document number: 001-04247 rev. *j page 19 of 40 39 pa6 or pktend gpio0 (input) i/o/z i (pa6) multiplexed pin whose function is selected by the ifconfig[1:0] bits. pa6 is a bidirectional i/o port pin. pktend is an input used to commit the fifo packet data to the endpoint and whose polarity is programmable via fifopinpolar[5]. gpio1 is a general purpose i/o signal. 40 pa7 or flagd or slcs# gpio1 (input) i/o/z i (pa7) multiplexed pin whose function is selected by the ifconfig[1:0] and portacfg[7] bits. pa7 is a bidirectional i/o port pin. flagd is a programmable slave-fifo output status flag signal. slcs# gates all other slave fifo enable/strobes gpio0 is a general purpose i/o signal. port b 18 pb0 or fd[0] dd0 i/o/z i (pb0) multiplexed pin whose function is select ed by ifconfig[1:0]. pb0 is a bidirectional i/o port pin. fd[0] is the bidirectional fifo/gpif data bus. dd0 is a bidirectional nand data bus signal. 19 pb1 or fd[1] dd1 i/o/z i (pb1) multiplexed pin whose function is select ed by ifconfig[1:0]. pb1 is a bidirectional i/o port pin. fd[1] is the bidirectional fifo/gpif data bus. dd1 is a bidirectional nand data bus signal. 20 pb2 or fd[2] dd2 i/o/z i (pb2) multiplexed pin whose function is select ed by ifconfig[1:0]. pb2 is a bidirectional i/o port pin. fd[2] is the bidirectional fifo/gpif data bus. dd2 is a bidirectional nand data bus signal. 21 pb3 or fd[3] dd3 i/o/z i (pb3) multiplexed pin whose function is select ed by ifconfig[1:0]. pb3 is a bidirectional i/o port pin. fd[3] is the bidirectional fifo/gpif data bus. dd3 is a bidirectional nand data bus signal. 22 pb4 or fd[4] dd4 i/o/z i (pb4) multiplexed pin whose function is select ed by ifconfig[1:0]. pb4 is a bidirectional i/o port pin. fd[4] is the bidirectional fifo/gpif data bus. dd4 is a bidirectional nand data bus signal. 23 pb5 or fd[5] dd5 i/o/z i (pb5) multiplexed pin whose function is select ed by ifconfig[1:0]. pb5 is a bidirectional i/o port pin. fd[5] is the bidirectional fifo/gpif data bus. dd5 is a bidirectional nand data bus signal. 24 pb6 or fd[6] dd6 i/o/z i (pb6) multiplexed pin whose function is select ed by ifconfig[1:0]. pb6 is a bidirectional i/o port pin. fd[6] is the bidirectional fifo/gpif data bus. dd6 is a bidirectional nand data bus signal. 25 pb7 or fd[7] dd7 i/o/z i (pb7) multiplexed pin whose function is select ed by ifconfig[1:0]. pb7 is a bidirectional i/o port pin. fd[7] is the bidirectional fifo/gpif data bus. dd7 is a bidirectional nand data bus signal. port d 45 pd0 or fd[8] ce0# i/o/z i (pd0) multiplexed pin whose function is selected by the ifconfig[1:0] and epxfifocfg.0 (wordwide) bits. fd[8] is the bidirectional fifo/gpif data bus. ce0# is a nand chip enable output signal. table 8. nx2lp-flex pin descriptions (continued) [6] 56-pin qfn pin number default pin name nand firmware usage pin type default state description
cy7c68033/cy7c68034 document number: 001-04247 rev. *j page 20 of 40 46 pd1 or fd[9] ce1# i/o/z i (pd1) multiplexed pin whose function is selected by the ifconfig[1:0] and epxfifocfg.0 (wordwide) bits. fd[9] is the bidirectional fifo/gpif data bus. ce1# is a nand chip enable output signal. 47 pd2 or fd[10] ce2# or gpio2 i/o/z i (pd2) multiplexed pin whose function is selected by the ifconfig[1:0] and epxfifocfg.0 (wordwide) bits. fd[10] is the bidirectiona l fifo/gpif data bus. ce2# is a nand chip enable output signal. gpio2 is a general purpose i/o signal. 48 pd3 or fd[11] ce3# or gpio3 i/o/z i (pd3) multiplexed pin whose function is selected by the ifconfig[1:0] and epxfifocfg.0 (wordwide) bits. fd[11] is the bidirectional fifo/gpif data bus. ce3# is a nand chip enable output signal. gpio3 is a general purpose i/o signal. 49 pd4 or fd[12] ce4# or gpio4 i/o/z i (pd4) multiplexed pin whose function is selected by the ifconfig[1:0] and epxfifocfg.0 (wordwide) bits. fd[12] is the bidirectiona l fifo/gpif data bus. ce4# is a nand chip enable output signal. gpio4 is a general purpose i/o signal. 50 pd5 or fd[13] ce5# or gpio5 i/o/z i (pd5) multiplexed pin whose function is selected by the ifconfig[1:0] and epxfifocfg.0 (wordwide) bits. fd[13] is the bidirectiona l fifo/gpif data bus. ce5# is a nand chip enable output signal. gpio5 is a general purpose i/o signal. 51 pd6 or fd[14] ce6# or gpio6 i/o/z i (pd6) multiplexed pin whose function is selected by the ifconfig[1:0] and epxfifocfg.0 (wordwide) bits. fd[14] is the bidirectiona l fifo/gpif data bus. ce6# is a nand chip enable output signal. gpio6 is a general purpose i/o signal. 52 pd7 or fd[15] ce7# or gpio7 i/o/z i (pd7) multiplexed pin whose function is selected by the ifconfig[1:0] and epxfifocfg.0 (wordwide) bits. fd[15] is the bidirectiona l fifo/gpif data bus. ce7# is a nand chip enable output signal. gpio7 is a general purpose i/o signal. power and ground 3, 7 avcc n/a power n/a analog v cc . connect this pin to 3.3 v power source. this signal provides power to the analog section of the chip. 6, 10 agnd n/a ground n/a analog ground . connect to ground with as short a path as possible. 11, 17, 27, 32, 43, 55 vcc n/a power n/a v cc . connect to 3.3 v power source. 12, 26, 28, 41, 53, 56 gnd n/a ground n/a ground . table 8. nx2lp-flex pin descriptions (continued) [6] 56-pin qfn pin number default pin name nand firmware usage pin type default state description
cy7c68033/cy7c68034 document number: 001-04247 rev. *j page 21 of 40 register summary nx2lp-flex register bit definitions are de scribed in the ez-usb trm in greater detail. some registers that are listed here and in the trm do not apply to the nx2lp-flex. they are kept here for consis tency reasons only. registers that do not apply to the nx2lp-f lex should be left at their default power up values. table 9. nx2lp-flex register summary hex size name description b7 b6 b5 b4 b3 b2 b1 b0 default access gpif waveform memories e400 128 wavedata gpif waveform descriptor 0, 1, 2, 3 data d7 d6 d5 d4 d3 d2 d1 d0 xxxxxxxx rw e480 128 reserved general configuration e50d gpcr2 general purpose configuration register 2 reserved reserved reserved full_spee d_only reserved reserved reserved reserved 00000000 r e600 1 cpucs cpu control & status 0 0 portcstb clkspd1 clkspd0 clkinv clkoe 8051res 00000010 rrbbbbbr e601 1 ifconfig interface configuration (ports, gpif, slave fifos) 1 3048 mhz 0 ifclkpol async gstate ifcfg1 ifcfg0 10000000 rw e602 1 pinflagsab [7] slave fifo flaga and flagb pin configuration flagb3 flagb2 flagb1 flagb0 flaga3 flaga2 flaga1 flaga0 00000000 rw e603 1 pinflagscd [7] slave fifo flagc and flagd pin configuration flagd3 flagd2 flagd1 flagd0 flagc3 flagc2 flagc1 flagc0 00000000 rw e604 1 fiforeset [7] restore fifos to default state nakall 0 0 0 ep3 ep2 ep1 ep0 xxxxxxxx w e605 1 breakpt breakpoint control 0 0 0 0 break bppulse bpen 0 00000000 rrrrbbbr e606 1 bpaddrh breakpoint address h a15 a14 a13 a12 a11 a10 a9 a8 xxxxxxxx rw e607 1 bpaddrl breakpoint address l a7 a6 a5 a4 a3 a2 a1 a0 xxxxxxxx rw e608 1 uart230 230 kbaud internally generated ref. clock 0 0 0 0 0 0 230uart1 230uart0 00000000 rrrrrrbb e609 1 fifopinpolar [7] slave fifo interface pins polarity 0 0 pktend sloe slrd slwr ef ff 00000000 rrbbbbbb e60a 1 revid chip revision rv7 rv6 rv5 rv4 rv3 rv2 rv1 rv0 reva 00000001 r e60b 1 revctl [7] chip revision control 0 0 0 0 0 0 dyn_out enh_pkt 00000000 rrrrrrbb udma e60c 1 gpifholdamount mstb hold time (for udma) 0 0 0 0 0 0 holdtime1 holdtime0 00000000 rrrrrrbb 3 reserved endpoint configuration e610 1 ep1outcfg endpoint 1-out configuration valid 0 type1 type0 0 0 0 0 10100000 brbbrrrr e611 1 ep1incfg endpoint 1-in configuration valid 0 type1 type0 0 0 0 0 10100000 brbbrrrr e612 1 ep2cfg endpoint 2 configuration valid dir type1 type0 size 0 buf1 buf0 10100010 bbbbbrbb e613 1 ep4cfg endpoint 4 configuration valid dir type1 type0 0 0 0 0 10100000 bbbbrrrr e614 1 ep6cfg endpoint 6 configuration valid dir type1 type0 size 0 buf1 buf0 11100010 bbbbbrbb e615 1 ep8cfg endpoint 8 configuration valid dir type1 type0 0 0 0 0 11100000 bbbbrrrr 2 reserved e618 1 ep2fifocfg [7] endpoint 2/slave fifo configuration 0 infm1 oep1 autoout autoin zerolenin 0 wordwide 00000101 rbbbbbrb e619 1 ep4fifocfg [7] endpoint 4/slave fifo configuration 0 infm1 oep1 autoout autoin zerolenin 0 wordwide 00000101 rbbbbbrb e61a 1 ep6fifocfg [7] endpoint 6/slave fifo configuration 0 infm1 oep1 autoout autoin zerolenin 0 wordwide 00000101 rbbbbbrb e61b 1 ep8fifocfg [7] endpoint 8/slave fifo configuration 0 infm1 oep1 autoout autoin zerolenin 0 wordwide 00000101 rbbbbbrb e61c 4 reserved e620 1 ep2autoinlenh [7] endpoint 2 autoin packet length h 0 0 0 0 0 pl10 pl9 pl8 00000010 rrrrrbbb e621 1 ep2autoinlenl [7] endpoint 2 autoin packet length l pl7 pl6 pl5 pl4 pl3 pl2 pl1 pl0 00000000 rw e622 1 ep4autoinlenh [7] endpoint 4 autoin packet length h 0 0 0 0 0 0 pl9 pl8 00000010 rrrrrrbb e623 1 ep4autoinlenl [7] endpoint 4 autoin packet length l pl7 pl6 pl5 pl4 pl3 pl2 pl1 pl0 00000000 rw e624 1 ep6autoinlenh [7] endpoint 6 autoin packet length h 0 0 0 0 0 pl10 pl9 pl8 00000010 rrrrrbbb e625 1 ep6autoinlen l [7] endpoint 6 autoin packet length l pl7 pl6 pl5 pl4 pl3 pl2 pl1 pl0 00000000 rw e626 1 ep8autoinlenh [7] endpoint 8 autoin packet length h 0 0 0 0 0 0 pl9 pl8 00000010 rrrrrrbb e627 1 ep8autoinlenl [7] endpoint 8 autoin packet length l pl7 pl6 pl5 pl4 pl3 pl2 pl1 pl0 00000000 rw e628 1 ecccfg ecc configuration 0 0 0 0 0 0 0 eccm 00000000 rrrrrrrb note 7. the register can only be reset, it cannot be set.
cy7c68033/cy7c68034 document number: 001-04247 rev. *j page 22 of 40 e629 1 eccreset ecc reset x x x x x x x x 00000000 w e62a 1 ecc1b0 ecc1 byte 0 address line15 line14 line13 line12 line11 line10 line9 line8 00000000 r e62b 1 ecc1b1 ecc1 byte 1 address line7 line6 line5 line4 line3 line2 line1 line0 00000000 r e62c 1 ecc1b2 ecc1 byte 2 address col5 col4 col3 col2 col1 col0 line17 line16 00000000 r e62d 1 ecc2b0 ecc2 byte 0 address line15 line14 line13 line12 line11 line10 line9 line8 00000000 r e62e 1 ecc2b1 ecc2 byte 1 address line7 line6 line5 line4 line3 line2 line1 line0 00000000 r e62f 1 ecc2b2 ecc2 byte 2 address col5 col4 col3 col2 col1 col0 0 0 00000000 r e630 h.s. 1 ep2fifopfh [8] endpoint 2/slave fifo programmable flag h decis pktstat in:pkts[2] out:pfc12 in:pkts[1] out:pfc11 in:pkts[0] out:pfc10 0 pfc9 pfc8 10001000 bbbbbrbb e630 f. s . 1 ep2fifopfh [8] endpoint 2/slave fifo programmable flag h decis pktstat out:pfc12 out:pfc11 out:pfc10 0 pfc9 in:pkts[2] out:pfc8 10001000 bbbbbrbb e631 h.s. 1 ep2fifopfl [8] endpoint 2/slave fifo programmable flag l pfc7 pfc6 pfc5 pfc4 pfc3 pfc2 pfc1 pfc0 00000000 rw e631 f. s 1 ep2fifopfl [8] endpoint 2/slave fifo programmable flag l in:pkts[1] out:pfc7 in:pkts[0] out:pfc6 pfc5 pfc4 pfc3 pfc2 pfc1 pfc0 00000000 rw e632 h.s. 1 ep4fifopfh [8] endpoint 4/slave fifo programmable flag h decis pktstat 0 in: pkts[1] out:pfc10 in: pkts[0] out:pfc9 0 0 pfc8 10001000 bbrbbrrb e632 f. s 1 ep4fifopfh [8] endpoint 4/slave fifo programmable flag h decis pktstat 0 out:pfc10 out:pfc9 0 0 pfc8 10001000 bbrbbrrb e633 h.s. 1 ep4fifopfl [8] endpoint 4/slave fifo programmable flag l pfc7 pfc6 pfc5 pfc4 pfc3 pfc2 pfc1 pfc0 00000000 rw e633 f. s 1 ep4fifopfl [8] endpoint 4/slave fifo programmable flag l in: pkts[1] out:pfc7 in: pkts[0] out:pfc6 pfc5 pfc4 pfc3 pfc2 pfc1 pfc0 00000000 rw e634 h.s. 1 ep6fifopfh [8] endpoint 6/slave fifo programmable flag h decis pktstat in:pkts[2] out:pfc12 in:pkts[1] out:pfc11 in:pkts[0] out:pfc10 0 pfc9 pfc8 00001000 bbbbbrbb e634 f. s 1 ep6fifopfh [8] endpoint 6/slave fifo programmable flag h decis pktstat out:pfc12 out:pfc11 out:pfc10 0 pfc9 in:pkts[2] out:pfc8 00001000 bbbbbrbb e635 h.s. 1 ep6fifopfl [8] endpoint 6/slave fifo programmable flag l pfc7 pfc6 pfc5 pfc4 pfc3 pfc2 pfc1 pfc0 00000000 rw e635 f. s 1 ep6fifopfl [8] endpoint 6/slave fifo programmable flag l in:pkts[1] out:pfc7 in:pkts[0] out:pfc6 pfc5 pfc4 pfc3 pfc2 pfc1 pfc0 00000000 rw e636 h.s. 1 ep8fifopfh [8] endpoint 8/slave fifo programmable flag h decis pktstat 0 in: pkts[1] out:pfc10 in: pkts[0] out:pfc9 0 0 pfc8 00001000 bbrbbrrb e636 f. s 1 ep8fifopfh [8] endpoint 8/slave fifo programmable flag h decis pktstat 0 out:pfc10 out:pfc9 0 0 pfc8 00001000 bbrbbrrb e637 h.s. 1 ep8fifopfl [8] endpoint 8/slave fifo programmable flag l pfc7 pfc6 pfc5 pfc4 pfc3 pfc2 pfc1 pfc0 00000000 rw e637 f. s 1 ep8fifopfl [8] endpoint 8/slave fifo programmable flag l in: pkts[1] out:pfc7 in: pkts[0] out:pfc6 pfc5 pfc4 pfc3 pfc2 pfc1 pfc0 00000000 rw 8 reserved e640 1 ep2isoinpkts ep2 (if iso) in packets per frame (1?3) aadj 0 0 0 0 0 inppf1 inppf0 00000001 brrrrrbb e641 1 ep4isoinpkts ep4 (if iso) in packets per frame (1?3) aadj 0 0 0 0 0 inppf1 inppf0 00000001 brrrrrrr e642 1 ep6isoinpkts ep6 (if iso) in packets per frame (1?3) aadj 0 0 0 0 0 inppf1 inppf0 00000001 brrrrrbb e643 1 ep8isoinpkts ep8 (if iso) in packets per frame (1?3) aadj 0 0 0 0 0 inppf1 inppf0 00000001 brrrrrrr e644 4 reserved e648 1 inpktend [8] force in packet end skip 0 0 0 ep3 ep2 ep1 ep0 xxxxxxxx w e649 7 outpktend [8] force out packet end skip 0 0 0 ep3 ep2 ep1 ep0 xxxxxxxx w interrupts e650 1 ep2fifoie [8] endpoint 2 slave fifo flag interrupt enable 0 0 0 0 edgepf pf ef ff 00000000 rw e651 1 ep2fifoirq [8, 9] endpoint 2 slave fifo flag interrupt request 0 0 0 0 0 pf ef ff 00000000 rrrrrbbb e652 1 ep4fifoie [8] endpoint 4 slave fifo flag interrupt enable 0 0 0 0 edgepf pf ef ff 00000000 rw e653 1 ep4fifoirq [8, 9] endpoint 4 slave fifo flag interrupt request 0 0 0 0 0 pf ef ff 00000000 rrrrrbbb e654 1 ep6fifoie [8] endpoint 6 slave fifo flag interrupt enable 0 0 0 0 edgepf pf ef ff 00000000 rw e655 1 ep6fifoirq [8, 9] endpoint 6 slave fifo flag interrupt request 0 0 0 0 0 pf ef ff 00000000 rrrrrbbb e656 1 ep8fifoie [8] endpoint 8 slave fifo flag interrupt enable 0 0 0 0 edgepf pf ef ff 00000000 rw e657 1 ep8fifoirq [8, 9] endpoint 8 slave fifo flag interrupt request 0 0 0 0 0 pf ef ff 00000000 rrrrrbbb e658 1 ibnie in-bulk-nak interrupt enable 0 0 ep8 ep6 ep4 ep2 ep1 ep0 00000000 rw e659 1 ibnirq [8] in-bulk-nak interrupt request 0 0 ep8 ep6 ep4 ep2 ep1 ep0 00xxxxxx rrbbbbbb e65a 1 nakie endpoint ping-nak/ibn interrupt enable ep8 ep6 ep4 ep2 ep1 ep0 0 ibn 00000000 rw table 9. nx2lp-flex register summary (continued) hex size name description b7 b6 b5 b4 b3 b2 b1 b0 default access notes 8. the register can only be reset, it cannot be set. 9. sfrs not part of the standard 8051 architecture.
cy7c68033/cy7c68034 document number: 001-04247 rev. *j page 23 of 40 e65b 1 nakirq [10] endpoint ping-nak/ibn interrupt request ep8 ep6 ep4 ep2 ep1 ep0 0 ibn xxxxxx0x bbbbbbrb e65c 1 usbie usb int enables 0 ep0ack hsgrant ures susp sutok sof sudav 00000000 rw e65d 1 usbirq [10] usb interrupt requests 0 ep0ack hsgrant ures susp sutok sof sudav 0xxxxxxx rbbbbbbb e65e 1 epie endpoint interrupt enables ep8 ep6 ep4 ep2 ep1out ep1in ep0out ep0in 00000000 rw e65f 1 epirq [10] endpoint interrupt requests ep8 ep6 ep4 ep2 ep1out ep1in ep0out ep0in 0 rw e660 1 gpifie [10] gpif interrupt enable 0 0 0 0 0 0 gpifwf gpifdone 00000000 rw e661 1 gpifirq [10] gpif interrupt request 0 0 0 0 0 0 gpifwf gpifdone 000000xx rw e662 1 usberrie usb error interrupt enables isoep8 isoep6 isoep4 isoep2 0 0 0 errlimit 00000000 rw e663 1 usberrirq [10] usb error interrupt requests isoep8 isoep6 isoep4 isoep2 0 0 0 errlimit 0000000x bbbbrrrb e664 1 errcntlim usb error counter and limit ec3 ec2 ec1 ec0 limit3 limit2 limit1 limit0 xxxx0100 rrrrbbbb e665 1 clrerrcnt clear error counter ec3:0 x x x x x x x x xxxxxxxx w e666 1 int2ivec interrupt 2 (usb) autovector 0 i2v4 i2v3 i2v2 i2v1 i2v0 0 0 00000000 r e667 1 int4ivec interrupt 4 (slave fifo & gpif) autovector 1 0 i4v3 i4v2 i4v1 i4v0 0 0 10000000 r e668 1 intset-up interrupt 2&4 setup 0 0 0 0 av2en 0 int4src av4en 00000000 rw e669 7 reserved input/output e670 1 portacfg i/o porta alternate configuration flagd slcs 0 0 0 0 int1 int0 00000000 rw e671 1 portccfg i/o portc alternate configuration gpifa7 gpifa6 gpifa5 gpifa4 gpifa3 gpifa2 gpifa1 gpifa0 00000000 rw e672 1 portecfg i/o porte alternate configuration gpifa8 t2ex int6 rxd1out rxd0out t2out t1out t0out 00000000 rw e673 4 xtalinsrc xtalin clock source 0 0 0 0 0 0 0 extclk 00000000 rrrrrrrb e677 1 reserved e678 1 i2cs i 2 c bus control & status start stop lastrd id1 id0 berr ack done 000xx000 bbbrrrrr e679 1 i2dat i 2 c bus data d7 d6 d5 d4 d3 d2 d1 d0 xxxxxxxx rw e67a 1 i2ctl i 2 c bus control 0 0 0 0 0 0 stopie 400khz 00000000 rw e67b 1 xautodat1 autoptr1 movx access, when aptren=1 d7 d6 d5 d4 d3 d2 d1 d0 xxxxxxxx rw e67c 1 xautodat2 autoptr2 movx access, when aptren=1 d7 d6 d5 d4 d3 d2 d1 d0 xxxxxxxx rw udma crc e67d 1 udmacrch [10] udma crc msb crc15 crc14 crc13 crc12 crc11 crc10 crc9 crc8 01001010 rw e67e 1 udmacrcl [10] udma crc lsb crc7 crc6 crc5 crc4 crc3 crc2 crc1 crc0 10111010 rw e67f 1 udmacrc- qualifier udma crc qualifier qenable 0 0 0 qstate qsignal2 qsignal1 qsignal0 00000000 brrrbbbb usb control e680 1 usbcs usb control & status hsm 0 0 0 discon nosynsof renum sigrsume x0000000 rrrrbbbb e681 1 suspend put chip into suspend x x x x x x x x xxxxxxxx w e682 1 wakeupcs wakeup control & status wu2 wu wu2pol wupol 0 dpen wu2en wuen xx000101 bbbbrbbb e683 1 togctl toggle control q s r i/o ep3 ep2 ep1 ep0 x0000000 rrrbbbbb e684 1 usbframeh usb frame count h 0 0 0 0 0 fc10 fc9 fc8 00000xxx r e685 1 usbframel usb frame count l fc7 fc6 fc5 fc4 fc3 fc2 fc1 fc0 xxxxxxxx r e686 1 microframe microframe count, 0?7 0 0 0 0 0 mf2 mf1 mf0 00000xxx r e687 1 fnaddr usb function address 0 fa6 fa5 fa4 fa3 fa2 fa1 fa0 0xxxxxxx r e688 2 reserved endpoints e68a 1 ep0bch [10] endpoint 0 byte count h (bc15) (bc14) (bc13) (bc12) (bc11) (bc10) (bc9) (bc8) xxxxxxxx rw e68b 1 ep0bcl [10] endpoint 0 byte count l (bc7) bc6 bc5 bc4 bc3 bc2 bc1 bc0 xxxxxxxx rw e68c 1 reserved e68d 1 ep1outbc endpoint 1 out byte count 0 bc6 bc5 bc4 bc3 bc2 bc1 bc0 0xxxxxxx rw e68e 1 reserved e68f 1 ep1inbc endpoint 1 in byte count 0 bc6 bc5 bc4 bc3 bc2 bc1 bc0 0xxxxxxx rw e690 1 ep2bch [10] endpoint 2 byte count h 0 0 0 0 0 bc10 bc9 bc8 00000xxx rw e691 1 ep2bcl [10] endpoint 2 byte count l bc7/skip bc6 bc5 bc4 bc3 bc2 bc1 bc0 xxxxxxxx rw e692 2 reserved e694 1 ep4bch [10] endpoint 4 byte count h 0 0 0 0 0 0 bc9 bc8 000000xx rw e695 1 ep4bcl [10] endpoint 4 byte count l bc7/skip bc6 bc5 bc4 bc3 bc2 bc1 bc0 xxxxxxxx rw e696 2 reserved e698 1 ep6bch [10] endpoint 6 byte count h 0 0 0 0 0 bc10 bc9 bc8 00000xxx rw e699 1 ep6bcl [10] endpoint 6 byte count l bc7/skip bc6 bc5 bc4 bc3 bc2 bc1 bc0 xxxxxxxx rw table 9. nx2lp-flex register summary (continued) hex size name description b7 b6 b5 b4 b3 b2 b1 b0 default access note 10. the register can only be reset, it cannot be set.
cy7c68033/cy7c68034 document number: 001-04247 rev. *j page 24 of 40 e69a 2 reserved e69c 1 ep8bch [11] endpoint 8 byte count h 0 0 0 0 0 0 bc9 bc8 000000xx rw e69d 1 ep8bcl [11] endpoint 8 byte count l bc7/skip bc6 bc5 bc4 bc3 bc2 bc1 bc0 xxxxxxxx rw e69e 2 reserved e6a0 1 ep0cs endpoint 0 control and status hsnak 0 0 0 0 0 busy stall 10000000 bbbbbbrb e6a1 1 ep1outcs endpoint 1 out control and status 0 0 0 0 0 0 busy stall 00000000 bbbbbbrb e6a2 1 ep1incs endpoint 1 in control and status 0 0 0 0 0 0 busy stall 00000000 bbbbbbrb e6a3 1 ep2cs endpoint 2 control and status 0 npak2 npak1 npak0 full empty 0 stall 00101000 rrrrrrrb e6a4 1 ep4cs endpoint 4 control and status 0 0 npak1 npak0 full empty 0 stall 00101000 rrrrrrrb e6a5 1 ep6cs endpoint 6 control and status 0 npak2 npak1 npak0 full empty 0 stall 00000100 rrrrrrrb e6a6 1 ep8cs endpoint 8 control and status 0 0 npak1 npak0 full empty 0 stall 00000100 rrrrrrrb e6a7 1 ep2fifoflgs endpoint 2 slave fifo flags 0 0 0 0 0 pf ef ff 00000010 r e6a8 1 ep4fifoflgs endpoint 4 slave fifo flags 0 0 0 0 0 pf ef ff 00000010 r e6a9 1 ep6fifoflgs endpoint 6 slave fifo flags 0 0 0 0 0 pf ef ff 00000110 r e6aa 1 ep8fifoflgs endpoint 8 slave fifo flags 0 0 0 0 0 pf ef ff 00000110 r e6ab 1 ep2fifobch endpoint 2 slave fifo total byte count h 0 0 0 bc12 bc11 bc10 bc9 bc8 00000000 r e6ac 1 ep2fifobcl endpoint 2 slave fifo total byte count l bc7 bc6 bc5 bc4 bc3 bc2 bc1 bc0 00000000 r e6ad 1 ep4fifobch endpoint 4 slave fifo total byte count h 0 0 0 0 0 bc10 bc9 bc8 00000000 r e6ae 1 ep4fifobcl endpoint 4 slave fifo total byte count l bc7 bc6 bc5 bc4 bc3 bc2 bc1 bc0 00000000 r e6af 1 ep6fifobch endpoint 6 slave fifo total byte count h 0 0 0 0 bc11 bc10 bc9 bc8 00000000 r e6b0 1 ep6fifobcl endpoint 6 slave fifo total byte count l bc7 bc6 bc5 bc4 bc3 bc2 bc1 bc0 00000000 r e6b1 1 ep8fifobch endpoint 8 slave fifo total byte count h 0 0 0 0 0 bc10 bc9 bc8 00000000 r e6b2 1 ep8fifobcl endpoint 8 slave fifo total byte count l bc7 bc6 bc5 bc4 bc3 bc2 bc1 bc0 00000000 r e6b3 1 sudptrh setup data pointer high address byte a15 a14 a13 a12 a11 a10 a9 a8 xxxxxxxx rw e6b4 1 sudptrl setup data pointer low address byte a7 a6 a5 a4 a3 a2 a1 0 xxxxxxx0 bbbbbbbr e6b5 1 sudptrctl setup data pointer auto mode 0 0 0 0 0 0 0 sdpauto 00000001 rw 2 reserved e6b8 8 set-updat 8 bytes of setup data d7 d6 d5 d4 d3 d2 d1 d0 xxxxxxxx r set-updat[0] = bmrequesttype set-updat[1] = bmrequest set-updat[2:3] = wvalue set-updat[4:5] = windex set-updat[6:7] = wlength gpif e6c0 1 gpifwfselect waveform selector singlewr1 singlewr0 singlerd1 singlerd0 fifowr1 fifowr0 fiford1 fiford0 11100100 rw e6c1 1 gpifidlecs gpif done, gpif idle drive mode done 0 0 0 0 0 0 idledrv 10000000 rw e6c2 1 gpifidlectl inactive bus, ctl states 0 0 ctl5 ctl4 ctl3 ctl2 ctl1 ctl0 11111111 rw e6c3 1 gpifctlcfg ctl drive type trictl 0 ctl5 ctl4 ctl3 ctl2 ctl1 ctl0 00000000 rw e6c4 1 gpifadrh [11] gpif address h 0 0 0 0 0 0 0 gpifa8 00000000 rw e6c5 1 gpifadrl [11] gpif address l gpifa7 gpifa6 gpifa5 gpifa4 gpifa3 gpifa2 gpifa1 gpifa0 00000000 rw flowstate e6c6 1 flowstate flowstate enable and selector fse 0 0 0 0 fs2 fs1 fs0 00000000 brrrrbbb e6c7 1 flowlogic flowstate logic lfunc1 lfunc0 terma2 terma1 terma0 termb2 termb1 termb0 00000000 rw table 9. nx2lp-flex register summary (continued) hex size name description b7 b6 b5 b4 b3 b2 b1 b0 default access note 11. the register can only be reset, it cannot be set.
cy7c68033/cy7c68034 document number: 001-04247 rev. *j page 25 of 40 e6c8 1 floweq0ctl ctl-pin states in flowstate (when logic = 0) ctl0e3 ctl0e2 ctl0e1 / ctl5 ctl0e0 / ctl4 ctl3 ctl2 ctl1 ctl0 00000000 rw e6c9 1 floweq1ctl ctl-pin states in flowstate (when logic = 1) ctl0e3 ctl0e2 ctl0e1 / ctl5 ctl0e0 / ctl4 ctl3 ctl2 ctl1 ctl0 00000000 rw e6ca 1 flowholdoff holdoff configuration hoperiod3 hoperiod2 hoperiod1 hoperiod 0 hostate hoctl2 hoctl1 hoctl0 00010010 rw e6cb 1 flowstb flowstate strobe configuration slave rdyasync ctltogl sustain 0 mstb2 mstb1 mstb0 00100000 rw e6cc 1 flowstbedge flowstate rising/falling edge configuration 0 0 0 0 0 0 falling rising 00000001 rrrrrrbb e6cd 1 flowstbperiod master-strobe half-period d7 d6 d5 d4 d3 d2 d1 d0 00000010 rw e6ce 1 gpiftcb3 [12] gpif transaction count byte 3 tc31 tc30 tc29 tc28 tc27 tc26 tc25 tc24 00000000 rw e6cf 1 gpiftcb2 [12] gpif transaction count byte 2 tc23 tc22 tc21 tc20 tc19 tc18 tc17 tc16 00000000 rw e6d0 1 gpiftcb1 [12] gpif transaction count byte 1 tc15 tc14 tc13 tc12 tc11 tc10 tc9 tc8 00000000 rw e6d1 1 gpiftcb0 [12] gpif transaction count byte 0 tc7 tc6 tc5 tc4 tc3 tc2 tc1 tc0 00000001 rw 2 reserved 00000000 rw reserved reserved 1 e6d2 1 ep2gpifflgsel [12] endpoint 2 gpif flag select 0 0 0 0 0 0 fs1 fs0 00000000 rw e6d3 1 ep2gpifpfstop endpoint 2 gpif stop transaction on prog. flag 0 0 0 0 0 0 0 fifo2flag 00000000 rw e6d4 1 ep2gpiftrig [12] endpoint 2 gpif trigger x x x x x x x x xxxxxxxx w 3 reserved reserved reserved e6da 1 ep4gpifflgsel [12] endpoint 4 gpif flag select 0 0 0 0 0 0 fs1 fs0 00000000 rw e6db 1 ep4gpifpfstop endpoint 4 gpif stop transaction on gpif flag 0 0 0 0 0 0 0 fifo4flag 00000000 rw e6dc 1 ep4gpiftrig [12] endpoint 4 gpif trigger x x x x x x x x xxxxxxxx w 3 reserved reserved reserved e6e2 1 ep6gpifflgsel [12] endpoint 6 gpif flag select 0 0 0 0 0 0 fs1 fs0 00000000 rw e6e3 1 ep6gpifpfstop endpoint 6 gpif stop transaction on prog. flag 0 0 0 0 0 0 0 fifo6flag 00000000 rw e6e4 1 ep6gpiftrig [12] endpoint 6 gpif trigger x x x x x x x x xxxxxxxx w 3 reserved reserved reserved e6ea 1 ep8gpifflgsel [12] endpoint 8 gpif flag select 0 0 0 0 0 0 fs1 fs0 00000000 rw e6eb 1 ep8gpifpfstop endpoint 8 gpif stop transaction on prog. flag 0 0 0 0 0 0 0 fifo8flag 00000000 rw e6ec 1 ep8gpiftrig [12] endpoint 8 gpif trigger x x x x x x x x xxxxxxxx w 3 reserved e6f0 1 xgpifsgldath gpif data h (16-bit mode only) d15 d14 d13 d12 d11 d10 d9 d8 xxxxxxxx rw e6f1 1 xgpifsgldatlx read/write gpif data l & trigger transaction d7 d6 d5 d4 d3 d2 d1 d0 xxxxxxxx rw e6f2 1 xgpifsgldatlnox read gpif data l, no transaction trigger d7 d6 d5 d4 d3 d2 d1 d0 xxxxxxxx r e6f3 1 gpifreadycfg internal rdy, sync/async, rdy pin states intrdy sas tcxrdy5 0 0 0 0 0 00000000 bbbrrrrr e6f4 1 gpifreadystat gpif ready status 0 0 rdy5 rdy4 rdy3 rdy2 rdy1 rdy0 00xxxxxx r e6f5 1 gpifabort abort gpif waveforms x x x x x x x x xxxxxxxx w e6f6 2 reserved endpoint buffers e740 64 ep0buf ep0-in/-out buffer d7 d6 d5 d4 d3 d2 d1 d0 xxxxxxxx rw e780 64 ep10utbuf ep1-out buffer d7 d6 d5 d4 d3 d2 d1 d0 xxxxxxxx rw e7c0 64 ep1inbuf ep1-in buffer d7 d6 d5 d4 d3 d2 d1 d0 xxxxxxxx rw 2048 reserved rw table 9. nx2lp-flex register summary (continued) hex size name description b7 b6 b5 b4 b3 b2 b1 b0 default access note 12. the register can only be reset, it cannot be set.
cy7c68033/cy7c68034 document number: 001-04247 rev. *j page 26 of 40 f000 1024 ep2fifobuf 512/1024-byte ep 2/slave fifo buffer (in or out) d7 d6 d5 d4 d3 d2 d1 d0 xxxxxxxx rw f400 512 ep4fifobuf 512 byte ep 4/slave fifo buffer (in or out) d7 d6 d5 d4 d3 d2 d1 d0 xxxxxxxx rw f600 512 reserved f800 1024 ep6fifobuf 512/1024-byte ep 6/slave fifo buffer (in or out) d7 d6 d5 d4 d3 d2 d1 d0 xxxxxxxx rw fc00 512 ep8fifobuf 512 byte ep 8/slave fifo buffer (in or out) d7 d6 d5 d4 d3 d2 d1 d0 xxxxxxxx rw fe00 512 reserved xxxx i2c configuration byte 0 discon 0 0 0 0 0 400 khz xxxxxxxx [14] n/a special function registers (sfrs) 80 1 ioa [13] port a (bit addressable) d7 d6 d5 d4 d3 d2 d1 d0 xxxxxxxx rw 81 1 sp stack pointer d7 d6 d5 d4 d3 d2 d1 d0 00000111 rw 82 1 dpl0 data pointer 0 l a7 a6 a5 a4 a3 a2 a1 a0 00000000 rw 83 1 dph0 data pointer 0 h a15 a14 a13 a12 a11 a10 a9 a8 00000000 rw 84 1 dpl1 [13] data pointer 1 l a7 a6 a5 a4 a3 a2 a1 a0 00000000 rw 85 1 dph1 [13] data pointer 1 h a15 a14 a13 a12 a11 a10 a9 a8 00000000 rw 86 1 dps [13] data pointer 0/1 select 0 0 0 0 0 0 0 sel 00000000 rw 87 1 pcon power control smod0 x 1 1 x x x idle 00110000 rw 88 1 tcon timer/counter control (bit addressable) tf1 tr1 tf0 tr0 ie1 it1 ie0 it0 00000000 rw 89 1 tmod timer/counter mode control gate ct m1 m0 gate ct m1 m0 00000000 rw 8a 1 tl0 timer 0 reload l d7 d6 d5 d4 d3 d2 d1 d0 00000000 rw 8b 1 tl1 timer 1 reload l d7 d6 d5 d4 d3 d2 d1 d0 00000000 rw 8c 1 th0 timer 0 reload h d15 d14 d13 d12 d11 d10 d9 d8 00000000 rw 8d 1 th1 timer 1 reload h d15 d14 d13 d12 d11 d10 d9 d8 00000000 rw 8e 1 ckcon [13] clock control x x t2m t1m t0m md2 md1 md0 00000001 rw 8f 1 reserved 90 1 iob [13] port b (bit addressable) d7 d6 d5 d4 d3 d2 d1 d0 xxxxxxxx rw 91 1 exif [13] external interrupt flag(s) ie5 ie4 i2cint usbnt 1 0 0 0 00001000 rw 92 1 mpage [13] upper addr byte of movx using @r0/@r1 a15 a14 a13 a12 a11 a10 a9 a8 00000000 rw 93 5 reserved 98 1 scon0 serial port 0 control (bit addressable) sm0_0 sm1_0 sm2_0 ren_0 tb8_0 rb8_0 ti_0 ri_0 00000000 rw 99 1 sbuf0 serial port 0 data buffer d7 d6 d5 d4 d3 d2 d1 d0 00000000 rw 9a 1 autoptrh1 [13] autopointer 1 address h a15 a14 a13 a12 a11 a10 a9 a8 00000000 rw 9b 1 autoptrl1 [13] autopointer 1 address l a7 a6 a5 a4 a3 a2 a1 a0 00000000 rw 9c 1 reserved 9d 1 autoptrh2 [13] autopointer 2 address h a15 a14 a13 a12 a11 a10 a9 a8 00000000 rw 9e 1 autoptrl2 [13] autopointer 2 address l a7 a6 a5 a4 a3 a2 a1 a0 00000000 rw 9f 1 reserved a0 1 ioc [13] port c (bit addressable) d7 d6 d5 d4 d3 d2 d1 d0 xxxxxxxx rw a1 1 int2clr [13] interrupt 2 clear x x x x x x x x xxxxxxxx w a2 1 int4clr [13] interrupt 4 clear x x x x x x x x xxxxxxxx w a3 5 reserved a8 1 ie interrupt enable (bit addressable) ea es1 et2 es0 et1 ex1 et0 ex0 00000000 rw a9 1 reserved aa 1 ep2468stat [13] endpoint 2,4,6,8 status flags ep8f ep8e ep6f ep6e ep4f ep4e ep2f ep2e 01011010 r ab 1 ep24fifoflgs [13] endpoint 2,4 slave fifo status flags 0 ep4pf ep4ef ep4ff 0 ep2pf ep2ef ep2ff 00100010 r ac 1 ep68fifoflgs [13] endpoint 6,8 slave fifo status flags 0 ep8pf ep8ef ep8ff 0 ep6pf ep6ef ep6ff 01100110 r ad 2 reserved af 1 autoptrset-up [13] autopointer 1&2 setup 0 0 0 0 0 aptr2inc aptr1inc aptren 00000110 rw b0 1 iod [13] port d (bit addressable) d7 d6 d5 d4 d3 d2 d1 d0 xxxxxxxx rw b1 1 ioe [13] port e (not bit addressable) d7 d6 d5 d4 d3 d2 d1 d0 xxxxxxxx rw b2 1 oea [13] port a output enable d7 d6 d5 d4 d3 d2 d1 d0 00000000 rw b3 1 oeb [13] port b output enable d7 d6 d5 d4 d3 d2 d1 d0 00000000 rw b4 1 oec [13] port c output enable d7 d6 d5 d4 d3 d2 d1 d0 00000000 rw b5 1 oed [13] port d output enable d7 d6 d5 d4 d3 d2 d1 d0 00000000 rw b6 1 oee [13] port e output enable d7 d6 d5 d4 d3 d2 d1 d0 00000000 rw b7 1 reserved table 9. nx2lp-flex register summary (continued) hex size name description b7 b6 b5 b4 b3 b2 b1 b0 default access notes 13. sfrs not part of the standard 8051 architecture. 14. if no nand is detected by the sie then the default is 00000000.
cy7c68033/cy7c68034 document number: 001-04247 rev. *j page 27 of 40 b8 1 ip interrupt priority (bit addressable) 1 ps1 pt2 ps0 pt1 px1 pt0 px0 10000000 rw b9 1 reserved ba 1 ep01stat [15] endpoint 0&1 status 0 0 0 0 0 ep1inbsy ep1outbs y ep0bsy 00000000 r bb 1 gpiftrig [15, 16] endpoint 2,4,6,8 gpif slave fifo trigger done 0 0 0 0 rw ep1 ep0 10000xxx brrrrbbb bc 1 reserved bd 1 gpifsgldath [15] gpif data h (16-bit mode only) d15 d14 d13 d12 d11 d10 d9 d8 xxxxxxxx rw be 1 gpifsgldatlx [15] gpif data l w/trigger d7 d6 d5 d4 d3 d2 d1 d0 xxxxxxxx rw bf 1 gpifsgldat lnox [15] gpif data l w/no trigger d7 d6 d5 d4 d3 d2 d1 d0 xxxxxxxx r c0 1 scon1 [15] serial port 1 control (bit addressable) sm0_1 sm1_1 sm2_1 ren_1 tb8_1 rb8_1 ti_1 ri_1 00000000 rw c1 1 sbuf1 [15] serial port 1 data buffer d7 d6 d5 d4 d3 d2 d1 d0 00000000 rw c2 6 reserved c8 1 t2con timer/counter 2 control (bit addressable) tf2 exf2 rclk tclk exen2 tr2 ct2 cprl2 00000000 rw c9 1 reserved ca 1 rcap2l capture for timer 2, auto-reload, up-counter d7 d6 d5 d4 d3 d2 d1 d0 00000000 rw cb 1 rcap2h capture for timer 2, auto-reload, up-counter d7 d6 d5 d4 d3 d2 d1 d0 00000000 rw cc 1 tl2 timer 2 reload l d7 d6 d5 d4 d3 d2 d1 d0 00000000 rw cd 1 th2 timer 2 reload h d15 d14 d13 d12 d11 d10 d9 d8 00000000 rw ce 2 reserved d0 1 psw program status word (bit addressable) cy ac f0 rs1 rs0 ov f1 p 00000000 rw d1 7 reserved d8 1 eicon [15] external interrupt control smod1 1 eresi resi int6 0 0 0 01000000 rw d9 7 reserved e0 1 acc accumulator (bit addressable) d7 d6 d5 d4 d3 d2 d1 d0 00000000 rw e1 7 reserved e8 1 eie [15] external interrupt enable(s) 1 1 1 ex6 ex5 ex4 ei2c eusb 11100000 rw e9 7 reserved f0 1 b b (bit addressable) d7 d6 d5 d4 d3 d2 d1 d0 00000000 rw f1 7 reserved f8 1 eip [15] external interrupt priority control 1 1 1 px6 px5 px4 pi2c pusb 11100000 rw f9 7 reserved table 9. nx2lp-flex register summary (continued) hex size name description b7 b6 b5 b4 b3 b2 b1 b0 default access r = read-only bit w = write-only bit b = both read/write bit r = all bits read-only w = all bits write-only notes 15. sfrs not part of the standard 8051 architecture. 16. if no nand is detected by the sie then the default is 00000000.
cy7c68033/cy7c68034 document number: 001-04247 rev. *j page 28 of 40 absolute maximum ratings exceeding maximum ratings may impair the useful life of the device. these user guidelines are not tested. storage temperature ................ ............... ?65 c to +150 c ambient temperature with power supplied ...................................... 0 c to +70 c supply voltage to ground potential .............?0.5 v to +4.0 v dc input voltage to any input pin ....... .............. .. +5.25 v [17] dc voltage applied to outputs in high z state ...................... ?0.5 v to v cc + 0.5 v power dissipation .................................................... 300 mw static discharge voltage ......................................... > 2000 v max output current, per i/o port ................................ 10 ma operating conditions t a (ambient temperature under bias) .......... 0 c to +70 c supply voltage .........................................+3.00 v to +3.60 v ground voltage ................................................................ 0 v f osc (oscillator or crystal frequency) ............. 24 mhz 100 ppm (parallel resonant) usb transceiver usb 2.0-compliant in full and high speed modes. ac electrical characteristics usb transceiver usb 2.0-compliant in full and high speed modes. dc characteristics parameter description conditions min typ max unit v cc supply voltage 3.00 3.3 3.60 v v cc ramp up 0 to 3.3 v 200 ? ? ? s v ih input high voltage 2 ? 5.25 v v il input low voltage ?0.5 ? 0.8 v v ih_x crystal input high voltage 2 ? 5.25 v v il_x crystal input low voltage ?0.5 ? 0.8 v i i input leakage current 0< v in < v cc ??10 ? a v oh output voltage high i out = 4 ma 2.4 ? ? v v ol output low voltage i out = ?4 ma ? ? 0.4 v i oh output current high ? ? 4 ma i ol output current low ? ? 4 ma c in input pin capacitance except d+/d? ? ? 10 pf d+/d? ? ? 15 pf i susp suspend current connected ? 300 380 [18] ? a cy7c68034 disconnected ? 100 150 [18] ? a suspend current connected ? 0.5 1.2 [18] ma cy7c68033 disconnected ? 0.3 1.0 [18] ma i cc supply current 8051 running, connected to usb hs ? 43 ? ma 8051 running, connected to usb fs ? 35 ? ma i unconfig unconfigured current before bm axpower granted by host ? 43 ? ma t reset reset time after valid power v cc min = 3.0 v 5.0 ? ? ms pin reset after powered on 200 ? ? ? s notes 17. applying power to i/o pins when the chip is not powered is not recommended. 18. .measured at max v cc , 25 c.
cy7c68033/cy7c68034 document number: 001-04247 rev. *j page 29 of 40 slave fifo asynchronous read figure 11. slave fifo asynchronous read timing diagram [19] slave fifo asynchronous write figure 12. slave fifo asynchronous write timing diagram [19] table 10. slave fifo asynchronous read parameters [20] parameter description min max unit t rdpwl slrd pulse width low 50 ? ns t rdpwh slrd pulse width high 50 ? ns t xflg slrd to flags output propagation delay ? 70 ns t xfd slrd to fifo data output propagation delay ? 15 ns t oeon sloe turn on to fifo data valid ? 10.5 ns t oeoff sloe turn off to fifo data hold ? 10.5 ns slrd flags t rdpwl t rdpwh sloe t xflg t xfd data t oeon t oeoff n+1 n data t sfd t fdh flags t xfd slwr/slcs# t wrpwh t wrpwl table 11. slave fifo asynchronous write parameters with inte rnally sourced ifclk [21] parameter description min max unit t wrpwl slwr pulse low 50 ? ns t wrpwh slwr pulse high 70 ? ns t sfd slwr to fifo data setup time 10 ? ns t fdh fifo data to slwr hold time 10 ? ns t xfd slwr to flags output propagation delay ? 70 ns notes 19. dashed lines denote signals with programmable polarity. 20. slave fifo asynchronous parameter values use internal ifclk setting at 48 mhz. 21. gpif asynchronous rdy x signals have a minimum setup time of 50 ns when using internal 48 mhz ifclk.
cy7c68033/cy7c68034 document number: 001-04247 rev. *j page 30 of 40 slave fifo asynchronous packet end strobe figure 13. slave fifo asynchronous packet end strobe timing diagram [22] slave fifo output enable figure 14. slave fifo output enable timing diagram [24] table 12. slave fifo asynchronous packet end strobe parameters [23] parameter description min max unit t pepwl pktend pulse width low 50 ? ns t pwpwh pktend pulse width high 50 ? ns t xflg pktend to flags output propagation delay ? 115 ns table 13. slave fifo output enable parameters parameter description min max unit t oeon sloe assert to fifo data output ? 10.5 ns t oeoff sloe deassert to fifo data hold ? 10.5 ns flags t xflg pktend t pepwl t pepwh sloe data t oeon t oeoff notes 22. sfrs not part of the standard 8051 architecture. 23. slave fifo asynchronous parameter val ues use internal ifclk setting at 48 mhz. 24. dashed lines denote signals with programmable polarity.
cy7c68033/cy7c68034 document number: 001-04247 rev. *j page 31 of 40 slave fifo address to flags/data figure 15. slave fifo address to flags/data timing diagram [25] slave fifo asynchronous address figure 16. slave fifo asynchronous address timing diagram [25] table 14. slave fifo address to flags/data parameters parameter description min max unit t xflg fifoadr[1:0] to flags output propagation delay ? 10.7 ns t xfd fifoadr[1:0] to fifodata ou tput propagation delay ? 14.3 ns fifoadr [1.0] data t xflg t xfd flags nn+1 slrd/slwr/pktend slcs/fifoadr [1:0] t sfa t fah table 15. slave fifo asynchronous address parameters [26] parameter description min max unit t sfa fifoadr[1:0] to slrd/slw r/pktend setup time 10 ? ns t fah rd/wr/pktend to fifoadr[ 1:0] hold time 10 ? ns notes 25. dashed lines denote signals with programmable polarity. 26. slave fifo asynchronous parameter values use internal ifclk setting at 48 mhz.
cy7c68033/cy7c68034 document number: 001-04247 rev. *j page 32 of 40 sequence diagram sequence diagram of a single and burst asynchronous read figure 17. slave fifo asynchronous read sequence and timing diagram [27] figure 18. slave fifo asynchronous read sequence of events diagram figure 17 shows the timing relati onship of the slave fifo signals during an asynchronous fifo read. it shows a single read followed by a burst read. at t = 0 the fifo address is stable and the slcs signal is asserted. at t = 1, sloe is asserted. this results in the data bus being driven. the data that is driven on to the bus is previous data, it data that was in the fi fo from a prior read cycle. at t = 2, slrd is asserted. the slrd must meet the minimum active pulse of t rdpwl and minimum deactive pulse width of t rdpwh . if slcs is used then, slcs must be in asserted with slrd or before slrd is asserted (that is the slcs and slrd signals must both be asserted to start a valid read condition). the data that is driven, after asserting slrd, is the updated data from the fifo. this data is valid after a propagation delay of t xfd from the activating edge of slrd. in figure 17 , data n is the first valid data read from the fifo. for data to appear on the data bus during t he read cycle (that is slrd is asserted), sloe must be in an asserted state. slrd and sloe can also be tied together. the same sequence of events is also shown for a burst read marked with t = 0 through 5. note in burst read mode, during sloe is assertion, the data bus is in a driven state and outputs the previous data. after slrd is asserted, the data from the fifo is driven on the data bus (sloe must also be asserted) and then the fifo pointer is incremented. slrd flags sloe data t rdpwh t rdpwl t oeon t xfd t xflg n data (x) t xfd n+1 t xfd t oeoff n+3 n+2 t oeoff t xflg t sfa t fah fifoadr slcs driven t xfd t oeon t rdpwh t rdpwl t rdpwh t rdpwl t rdpwh t rdpwl t fah t sfa n t=0 t=0 t=1 t=7 t=2 t=3 t=4 t=5 t=6 t=1 t=2 t=3 t=4 nn sloe slrd fifo pointer n+3 fifo data bus not driven driven: x n not driven sloe n n+2 n+3 slrd n n+1 slrd n+1 slrd n+1 n+2 slrd n+2 slrd n+2 n+1 sloe not driven sloe n n+1 n+1 note 27. dashed lines denote signals with programmable polarity.
cy7c68033/cy7c68034 document number: 001-04247 rev. *j page 33 of 40 sequence diagram of a single and burst asynchronous write figure 19. slave fifo asynchronous write sequence and timing diagram [28] figure 19 shows the timing relationship of the slave fifo write in an asynchronous mode. the diagram shows a single write followed by a burst write of three bytes and committing the 4-byte-short packet using pktend. at t = 0 the fifo address is applied, insuring that it meets the setup time of t sfa . if slcs is used, it must also be asserted (slcs may be tied low in some applications). at t = 1 slwr is asserted. slwr must meet the minimum active pulse of t wrpwl and minimum de-active pulse width of t wrpwh . if the slcs is used, it must be in asserted with slwr or before slwr is asserted. at t = 2, data must be present on the bus t sfd before the deasserting edge of slwr. at t = 3, deasserting slwr causes the data to be written from the data bus to the fifo and then increments the fifo pointer. the fifo flag is also updated after t xflg from the deasserting edge of slwr. the same sequence of events are shown for a burst write and is indicated by the timing marks of t = 0 through 5. note in the burst write mode, afte r slwr is deasserted, the data is written to the fifo and then the fifo pointer is incremented to the next byte in the fifo. the fifo pointer is post incremented. as shown in figure 19 after the four bytes are written to the fifo and slwr is deasserted, the short 4-byte packet can be committed to the host using th e pktend. the external device should be designed to not assert slwr and the pktend signal at the same time. it should be designed to assert the pktend after slwr is deasserted and met the minimum de-asserted pulse width. the fifoaddr lines are to be held constant during the pktend assertion. pktend slwr flags data t wrpwh t wrpwl t xflg n t sfd n+1 t xflg t sfa t fah fifoadr slcs t wrpwh t wrpwl t wrpwh t wrpwl t wrpwh t wrpwl t fah t sfa t fdh t sfd n+2 t fdh t sfd n+3 t fdh t sfd t fdh t pepwh t pepwl t=0 t=2 t =1 t=3 t=0 t=2 t=1 t=3 t=6 t=9 t=5 t=8 t=4 t=7 note 28. dashed lines denote signals with programmable polarity.
cy7c68033/cy7c68034 document number: 001-04247 rev. *j page 34 of 40 ordering code definitions ordering information ordering code description silicon for battery-powered applications cy7c68034-56ltxc 8 8 mm, 56-pin qfn (sawn) cy7c68034-56ltxi 8 8 mm, 56-pin qfn (sawn) silicon for non-battery-powered applications cy7c68033-56ltxc 8 8 mm, 56-pin qfn (sawn) development kit cy3686 ez-usb nx2lp-flex development kit x = t or blank t = tape and reel; blank = tube temperature range: x = c or i c = commercial; i = industrial x = pb-free (rohs compliant) package type: lt = qfn package no. of pins in package: 56-pin part number: 03x = 034 or 033 family code: 68 = usb technology code: c = cmos marketing code: 7 = sram company id: cy = cypress 7 cy 68 - lt x x x 56 03x c
cy7c68033/cy7c68034 document number: 001-04247 rev. *j page 35 of 40 package diagrams figure 20. 56-pin qfn (8 8 1.0 mm) lt56b 4.5 5.2 epad (sawn), 001-53450 001-53450 *b
cy7c68033/cy7c68034 document number: 001-04247 rev. *j page 36 of 40 pcb layout recommendations follow these recommendations [29] to ensure reliable high performance operation: at least a four-layer impedance controlled boards is recommended to maintain signal quality. specify impedance targets (ask your board vendor what they can achieve) to meet usb specifications. to control impedance, maintain trace widths and trace spacing. minimize any stubs to avoid reflected signals. connections between the usb connector shell and signal ground must be done near the usb connector. bypass/flyback caps on vbus, near connector, are recommended. dplus and dminus trace lengths should be kept to within 2 mm of each other in lengt h, with preferred length of 20?30 mm. maintain a solid ground plane under the dplus and dminus traces. do not allow the plane to be split under these traces. no vias should be placed on the dplus or dminus trace routing unless absolutely necessary. isolate the dplus and dminus traces from all other signal traces as much as possible. quad flat package no leads (qfn) package design notes electrical contact of the part to the printed circuit board (pcb) is made by soldering the leads on the bottom surface of the package to the pcb. therefore, special attention is required to the heat transfer area below the package to provide a good thermal bond to the circuit board. design a copper (cu) fill into the pcb as a thermal pad under the package. heat is transferred from the nx2lp-flex to the pcb through the device?s metal paddle on the bottom side of the package. it is then conducted from the pcb?s thermal pad to the inner ground plane by a 5 5 array of vias. a via is a plated through hole in the pcb with a finished diameter of 13 mil. the qfn?s metal die paddle must be soldered to the pcb?s thermal pad. solder mask is placed on the board top side over each via to resist solder flow into the via. the mask on the top side also minimizes outgassing during the solder reflow process. for further information on this package design, refer to the application note application note for surface mount assembly of amkor?s eutectic and lead-free csp nl ? wafer level chip scale packages . this application note provides detailed information on board mounting guidelines, soldering flow, rework process, and so on. note 29. source for recommendations: ez-usb fx2?pcb design recommendations and high speed usb platform design guidelines .
cy7c68033/cy7c68034 document number: 001-04247 rev. *j page 37 of 40 figure 21 displays a cross-sectional area underneath the package. the cr oss section is of only one vi a. the solder paste template needs to be designed to enable at least 50% solder coverage. t he thickness of the solder paste template should be 5 mil. it is recommended that ?no clean? type 3 solder paste is used for mounting the part. nitrogen purge is recommended during reflow. figure 22 is a plot of the solder mask pattern and figure 23 displays an x-ray image of the asse mbly (darker areas indicate solder). figure 21. cross-section of the area underneath the qfn package. figure 22. plot of the solder mask (white area) figure 23. x-ray image of the assembly 0.017? dia solder mask cu fill cu fill pcb material pcb material 0.013? dia via hole for thermally connecting the qfn to the circuit board ground plane. this figure only shows the top three layers of the circuit board: top solder, pcb dielectric, and the ground plane.
cy7c68033/cy7c68034 document number: 001-04247 rev. *j page 38 of 40 acronyms document conventions units of measure acronym description asic application specific integrated circuit cpu central processing unit dsp digital signal processor ecc error correcting codes eeprom electrically erasable programmable read only memory fifo first in first out gpif general programmable interface gpio general purpose input/output i/o input/output lan local area network lsb least-significant bit msb most-significant bit pll phase locked loop pcb printed circuit board psoc programmable system-on-chip qfn quad flat no leads ram random access memory rom read only memory scl serial clock sda serial data line sie serial interface engine usb universal serial bus symbol unit of measure c degree celsius khz kilohertz mhz megahertz a microampere s microsecond w microwatt ma milliampere mm millimeter ms millisecond mv millivolt mw milliwatt ns nanosecond ? ohms % percent pf picofarad ppm parts per million vvolt
cy7c68033/cy7c68034 document number: 001-04247 rev. *j page 39 of 40 document history page document title: cy7c68033/cy7c68034, ez-usb ? nx2lp-flex? flexible usb nand flash controller document number: 001-04247 rev. ecn no. submission date orig. of change description of change ** 388499 see ecn gir preliminary draft *a 394699 see ecn xut minor change: upload data shee t to external website. publicly announcing the parts. no physical changes to document were made *b 400518 see ecn gir took ?preliminary? off the top of all pages. corrected the first bulleted item. corrected figure 3-2 caption. added new logo *c 433952 see ecn rgl added i 2 c functionality *d 498295 see ecn kku updated data sheet format changed in/output refere nce from i/o to i/o changed set-up to setup changed ifclk and clkout pins to gpio8 and gpio9. removed external ifclk *e 2717536 06/11/2009 dpt added 56 qfn (8 x 8 mm) package diagram and added cy7c68033-56ltxc and cy7c68034-56ltxc part information in the ordering information table *f 2728424 07/02/2009 gnkk updated revision in the footer *g 2896281 03/19/2010 odc removed inactive parts.updated package diagram. added table of contents.updated links in sales, solutions and legal information. *h 2933818 05/18/2010 shah / aesa added contents and acronyms updated default nand firmware features formatted table footnotes. *i 3349690 08/25/2011 odc updated package diagrams (removed package drawing 51-85144). added units of measure . updated in new template. *j 3668026 07/06/2012 gaya updated ordering information with part number cy7c68034-56ltxi.
document number: 001-04247 rev. *j revised july 6, 2012 page 40 of 40 all products and company names mentioned in this document may be the trademarks of their respective holders. cy7c68033/cy7c68034 ? cypress semiconductor corporation, 2005-2012. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory optical & image sensing cypress.com/go/image psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 5

▲Up To Search▲

Price & Availability of CY7C6803312

	To Download CY7C6803312 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .